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add rest of basic mov instructions

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iris
2026-06-12 21:53:22 -04:00
parent 397176759d
commit 715a50b1fa
6 changed files with 109 additions and 36 deletions
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src/arch/x86_64/encode.rs
+51 -18
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@@ -28,7 +28,7 @@ impl Code {
if src.requires_rex() || dst.requires_rex() {
self.bytes.push(rex(width, src, 0, dst));
}
self.bytes.push(0x88 | width.gt8() as u8);
self.bytes.push(0x88 | width.not8());
self.bytes.push(modrm_regs(src, dst));
}
RegImmMem::Imm(src) => {
@@ -49,15 +49,42 @@ impl Code {
if dst.requires_rex() {
self.bytes.push(rex(dst.width(), 0, 0, dst));
}
let opcode = 0xb0 | ((dst.width().gt8() as u8) << 3);
self.bytes.push(opcode | dst.base());
self.bytes.push(0xb0 | (dst.not8() << 3) | dst.base());
self.imm(src, dst.width());
}
}
RegImmMem::Mem(src) => todo!(),
RegImmMem::Mem(src) => {
if src.width != dst.width() {
return Err("register & memory sizes don't match".into());
}
if dst.high() && src.reg.gt8() {
return Err("registers incompatible (REX)".into());
}
self.prefix32(&src)?;
self.prefix16(dst);
if dst.requires_rex() | src.reg.gt8() {
self.bytes.push(rex(dst.width(), dst, 0, src.reg));
}
self.bytes.push(0x8a | dst.not8());
self.modrm_regdisp(dst, src);
}
},
RegMem::Mem(dst) => match src {
RegImmMem::Reg(src) => todo!(),
RegImmMem::Reg(src) => {
if src.width() != dst.width {
return Err("register & memory sizes don't match".into());
}
if src.high() && dst.reg.gt8() {
return Err("registers incompatible (REX)".into());
}
self.prefix32(&dst)?;
self.prefix16(src);
if src.requires_rex() | dst.reg.gt8() {
self.bytes.push(rex(src.width(), src, 0, dst.reg));
}
self.bytes.push(0x88 | src.not8());
self.modrm_regdisp(src, dst);
}
RegImmMem::Imm(src) => {
let encode_width = dst.width.min(Width::B32);
let src_width = if dst.width == Width::B64 {
@@ -71,17 +98,13 @@ impl Code {
if src_width > dst.width {
return Err("source cannot fit in destination".into());
}
match dst.reg.width() {
Width::B8 | Width::B16 => return Err("invalid register width".into()),
Width::B32 => self.bytes.push(0x67),
Width::B64 => (),
}
self.prefix32(&dst)?;
self.prefix16(encode_width);
if dst.reg.requires_mem_rex() || dst.width == Width::B64 {
self.bytes.push(rex(dst.width, 0, 0, dst.reg));
}
self.bytes.push(0xc6 | (encode_width != Width::B8) as u8);
self.modrm_regdisp(dst.reg, dst.disp);
self.bytes.push(0xc6 | encode_width.not8());
self.modrm_regdisp(None, dst);
self.imm(src, encode_width);
}
RegImmMem::Mem(_) => return Err("cannot move memory to memory".into()),
@@ -170,23 +193,33 @@ impl Code {
}
}
fn modrm_regdisp(&mut self, reg: Reg, disp: i32) {
fn prefix32(&mut self, mem: &Mem) -> Result<(), CompilerMsg> {
match mem.reg.width() {
Width::B8 | Width::B16 => return Err("invalid register width".into()),
Width::B32 => self.bytes.push(0x67),
Width::B64 => (),
}
Ok(())
}
fn modrm_regdisp(&mut self, reg: impl Into<Option<Reg>>, mem: Mem) {
const I8_MIN: i32 = i8::MIN as i32;
const I8_MAX: i32 = i8::MAX as i32;
let mod_ = match disp {
let mod_ = match mem.disp {
0 => 0b00,
I8_MIN..=I8_MAX => 0b01,
_ => 0b10,
};
self.bytes.push(modrm(mod_, 0, reg.base()));
if reg.base() == rsp.base() {
let r = reg.into().map(|r| Reg::base(&r)).unwrap_or(0);
self.bytes.push(modrm(mod_, r, mem.reg.base()));
if mem.reg.base() == rsp.base() {
// SIB
self.bytes.push(0x24);
}
match mod_ {
0b00 => (),
0b01 => self.bytes.push(disp as u8),
0b10 => self.bytes.extend(disp.to_le_bytes()),
0b01 => self.bytes.push(mem.disp as u8),
0b10 => self.bytes.extend(mem.disp.to_le_bytes()),
_ => unreachable!(),
}
}