251 lines
8.8 KiB
Rust
251 lines
8.8 KiB
Rust
use super::*;
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use crate::backend::Symbol;
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type ERes = Result<(), CompilerMsg>;
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/// machine code
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#[derive(Default)]
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pub struct Code {
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pub(super) bytes: Vec<u8>,
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pub(super) missing: Vec<(usize, Symbol)>,
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}
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impl Code {
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pub fn mov(&mut self, dst: impl Into<RegMem>, src: impl Into<RegImmMem>) -> ERes {
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let dst = dst.into();
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let src = src.into();
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match dst {
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RegMem::Reg(mut dst) => match src {
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RegImmMem::Reg(src) => {
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if dst.width() != src.width() {
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return Err("src and dst are not same width".into());
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}
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if dst.incompatible(&src) {
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return Err("incompatible registers due to rex".into());
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}
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let width = dst.width();
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self.prefix16(width);
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if src.requires_rex() || dst.requires_rex() {
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self.bytes.push(rex(width, src, 0, dst));
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}
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self.bytes.push(0x88 | width.not8());
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self.bytes.push(modrm_regs(src, dst));
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}
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RegImmMem::Imm(src) => {
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let src_width = src.width_unsigned()?;
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if src_width > dst.width() {
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return Err("immediate cannot fit in register".into());
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}
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self.prefix16(dst);
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if dst.width() == Width::B64 && src_width <= Width::B32 && src.0 < 0 {
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// use different op that sign extends for less bytes
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self.bytes
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.extend([rex(dst.width(), 0, 0, dst), 0xc7, 0xc0 | dst.base()]);
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self.imm(src, Width::B32);
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} else {
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if src_width <= Width::B32 {
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dst = dst.lower64();
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}
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if dst.requires_rex() {
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self.bytes.push(rex(dst.width(), 0, 0, dst));
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}
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self.bytes.push(0xb0 | (dst.not8() << 3) | dst.base());
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self.imm(src, dst.width());
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}
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}
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RegImmMem::Mem(src) => {
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if src.width != dst.width() {
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return Err("register & memory sizes don't match".into());
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}
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if dst.high() && src.reg.gt8() {
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return Err("registers incompatible (REX)".into());
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}
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self.prefix32(&src)?;
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self.prefix16(dst);
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if dst.requires_rex() | src.reg.gt8() {
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self.bytes.push(rex(dst.width(), dst, 0, src.reg));
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}
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self.bytes.push(0x8a | dst.not8());
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self.modrm_regdisp(dst, src);
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}
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},
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RegMem::Mem(dst) => match src {
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RegImmMem::Reg(src) => {
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if src.width() != dst.width {
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return Err("register & memory sizes don't match".into());
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}
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if src.high() && dst.reg.gt8() {
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return Err("registers incompatible (REX)".into());
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}
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self.prefix32(&dst)?;
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self.prefix16(src);
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if src.requires_rex() | dst.reg.gt8() {
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self.bytes.push(rex(src.width(), src, 0, dst.reg));
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}
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self.bytes.push(0x88 | src.not8());
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self.modrm_regdisp(src, dst);
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}
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RegImmMem::Imm(src) => {
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let encode_width = dst.width.min(Width::B32);
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let src_width = if dst.width == Width::B64 {
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src.width_signed()
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} else {
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src.width_unsigned()
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}?;
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if src_width == Width::B64 {
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return Err("cannot move 64 bit immediate into memory".into());
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}
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if src_width > dst.width {
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return Err("source cannot fit in destination".into());
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}
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self.prefix32(&dst)?;
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self.prefix16(encode_width);
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if dst.reg.requires_mem_rex() || dst.width == Width::B64 {
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self.bytes.push(rex(dst.width, 0, 0, dst.reg));
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}
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self.bytes.push(0xc6 | encode_width.not8());
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self.modrm_regdisp(None, dst);
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self.imm(src, encode_width);
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}
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RegImmMem::Mem(_) => return Err("cannot move memory to memory".into()),
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},
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}
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Ok(())
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}
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pub fn push(&mut self, reg: impl Into<RegImmMem>) -> ERes {
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match reg.into() {
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RegImmMem::Reg(reg) => match reg.width() {
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Width::B64 => {
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if reg.gt8() {
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self.bytes.push(0x41);
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}
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self.bytes.push(0x50 | reg.base());
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}
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Width::B16 => {}
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_ => return Err("register must be 64 or 16 bit".into()),
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},
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RegImmMem::Imm(imm) => match imm.width_unsigned()? {
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Width::B8 => {
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self.bytes.push(0x6a);
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self.bytes.push(imm.0 as u8);
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}
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Width::B16 | Width::B32 => {
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self.bytes.push(0x68);
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self.bytes.extend((imm.0 as u32).to_le_bytes());
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}
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Width::B64 => return Err("immediate must be 32 bit or less".into()),
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},
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RegImmMem::Mem(mem) => todo!(),
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}
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Ok(())
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}
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pub fn pop(&mut self, reg: Reg) -> ERes {
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match reg.width() {
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Width::B64 | Width::B16 => (),
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_ => return Err("register must be 64 or 16 bit".into()),
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}
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self.prefix16(reg);
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if reg.gt8() {
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self.bytes.push(0x41);
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}
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self.bytes.push(0x58 | reg.base());
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Ok(())
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}
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pub fn lea(&mut self, dst: Reg, sym: Symbol) {
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self.bytes
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.extend([rex(1, dst, 0, 0), 0x8d, modrm_disp32(dst)]);
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self.sym_offset4(sym);
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}
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pub fn int(&mut self, code: u8) {
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self.bytes.extend([0xcd, code])
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}
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pub fn syscall(&mut self) {
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self.bytes.extend([0x0f, 0x05])
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}
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pub fn call(&mut self, sym: Symbol) {
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self.bytes.push(0xe8);
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self.sym_offset4(sym);
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}
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pub fn call_mem(&mut self, sym: Symbol) {
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self.bytes.extend([0xff, 0x15]);
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self.sym_offset4(sym);
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}
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pub fn ret(&mut self) {
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self.bytes.push(0xc3);
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}
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pub fn sub(&mut self) {
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// sub esp 40 iirc
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self.bytes.extend([0x48, 0x83, 0xec, 0x28]);
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}
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fn prefix16(&mut self, width: impl Into<Width>) {
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if width.into() == Width::B16 {
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self.bytes.push(0x66);
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}
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}
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fn prefix32(&mut self, mem: &Mem) -> Result<(), CompilerMsg> {
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match mem.reg.width() {
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Width::B8 | Width::B16 => return Err("invalid register width".into()),
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Width::B32 => self.bytes.push(0x67),
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Width::B64 => (),
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}
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Ok(())
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}
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fn modrm_regdisp(&mut self, reg: impl Into<Option<Reg>>, mem: Mem) {
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const I8_MIN: i32 = i8::MIN as i32;
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const I8_MAX: i32 = i8::MAX as i32;
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let mod_ = match mem.disp {
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0 => 0b00,
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I8_MIN..=I8_MAX => 0b01,
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_ => 0b10,
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};
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let r = reg.into().map(|r| Reg::base(&r)).unwrap_or(0);
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self.bytes.push(modrm(mod_, r, mem.reg.base()));
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if mem.reg.base() == rsp.base() {
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// SIB
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self.bytes.push(0x24);
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}
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match mod_ {
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0b00 => (),
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0b01 => self.bytes.push(mem.disp as u8),
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0b10 => self.bytes.extend(mem.disp.to_le_bytes()),
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_ => unreachable!(),
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}
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}
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/// inserts a 32 bit offset from a symbol
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fn sym_offset4(&mut self, sym: Symbol) {
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let pos = self.bytes.len();
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self.bytes.extend([0; 4]);
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self.missing.push((pos, sym));
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}
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pub fn extend(&mut self, other: &Code) {
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let pos = self.bytes.len();
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self.bytes.extend(&other.bytes);
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self.missing
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.extend(other.missing.iter().map(|&(p, s)| (pos + p, s)));
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}
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fn imm(&mut self, imm: Imm, width: Width) {
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self.bytes.extend(&imm.0.to_le_bytes()[..width.bytes()]);
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}
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}
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pub fn encode(f: impl FnOnce(&mut Code) -> Result<(), CompilerMsg>) -> Result<Code, CompilerMsg> {
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let mut code = Code::default();
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f(&mut code)?;
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Ok(code)
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}
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