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iris
2026-06-12 17:40:48 -04:00
parent 51bdc5c684
commit 397176759d
1 changed files with 1 additions and 0 deletions
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src/arch/x86_64/encode.rs
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@@ -38,6 +38,7 @@ impl Code {
} }
self.prefix16(dst); self.prefix16(dst);
if dst.width() == Width::B64 && src_width <= Width::B32 && src.0 < 0 { if dst.width() == Width::B64 && src_width <= Width::B32 && src.0 < 0 {
// use different op that sign extends for less bytes
self.bytes self.bytes
.extend([rex(dst.width(), 0, 0, dst), 0xc7, 0xc0 | dst.base()]); .extend([rex(dst.width(), 0, 0, dst), 0xc7, 0xc0 | dst.base()]);
self.imm(src, Width::B32); self.imm(src, Width::B32);