x86_64 compiler + elf output (can compile code that returns exit code)

This commit is contained in:
2026-06-03 01:50:43 -04:00
parent 473ddab0d4
commit 380a0f977a
11 changed files with 422 additions and 76 deletions
+238 -32
View File
@@ -1,32 +1,120 @@
use crate::io::CompilerMsg;
pub struct Asm {
pub instrs: Vec<Instr>,
}
pub enum Instr {
Mov { dst: RegMode, src: RegImm },
Int { code: u8 },
}
pub enum RegImm {
Reg(RegMode),
Imm(u64),
}
pub struct Reg(u8);
pub struct RegMode {
reg: Reg,
mode: BitMode,
width: BitWidth,
high: bool,
}
impl Asm {
pub fn compile(&self, out: &mut Vec<u8>) -> Result<(), CompilerMsg> {
for instr in &self.instrs {
instr.compile(out)?;
}
Ok(())
}
}
impl Instr {
pub fn compile(&self, out: &mut Vec<u8>) -> Result<(), CompilerMsg> {
match self {
Instr::Mov { dst, src } => {
let width = dst.width;
if width == BitWidth::B16 {
out.push(0x66);
}
let dst8 = dst.gt8();
let b64 = width == BitWidth::B64;
let b8 = width == BitWidth::B8;
let src8 = if let RegImm::Reg(src) = src {
src.gt8()
} else {
false
};
if dst8 || src8 || b64 || (dst.gt4() && !dst.high) {
out.push(0x40 | dst8 as u8 | ((b64 as u8) << 3) | ((src8 as u8) << 2));
}
match src {
RegImm::Reg(src) => {
if dst.width != src.width {
return Err("src and dst are not the same size".into());
}
out.push(0x88 | !b8 as u8);
let modrm = 0b11_000_000 | (src.base() << 3) | dst.base();
out.push(modrm);
}
&RegImm::Imm(imm) => {
if imm > width.max() {
return Err("immediate cannot fit in register".into());
}
out.push(0xb0 | ((!b8 as u8) << 3) | dst.base());
out.extend(&imm.to_le_bytes()[..width.bytes()]);
}
}
}
Instr::Int { code } => out.extend([0xcd, *code]),
}
Ok(())
}
}
impl RegMode {
pub fn base(&self) -> u8 {
self.reg.0 & 0b111
}
/// checks if register is not one of the first 8 (0-7)
pub fn gt8(&self) -> bool {
self.reg.0 >= 0b1000
}
pub fn gt4(&self) -> bool {
self.reg.0 >= 0b0100
}
}
macro_rules! def_regs {
($($val:literal $reg:ident: $B64:literal $B32:literal $B16:literal $B8:literal $($B16H:literal)?,)*) => {
impl Reg {
($($val:literal : $B64:ident $B32:ident $B16:ident $B8:ident $($B8H:ident=$hval:expr)?,)*) => {
#[allow(non_upper_case_globals)]
pub mod reg {
use super::{RegMode, BitWidth, Reg};
$(
pub const $reg: u8 = $val;
pub const $B64: RegMode = RegMode { reg: Reg($val), width: BitWidth::B64, high: false };
pub const $B32: RegMode = RegMode { reg: Reg($val), width: BitWidth::B32, high: false };
pub const $B16: RegMode = RegMode { reg: Reg($val), width: BitWidth::B16, high: false };
pub const $B8 : RegMode = RegMode { reg: Reg($val), width: BitWidth::B8, high: false };
$(
pub const $B8H: RegMode = RegMode { reg: $hval.reg, width: BitWidth::B8, high: true };
)?
)*
}
impl RegMode {
pub fn parse(s: &str) -> Option<Self> {
let (reg, mode) = match s.to_lowercase().as_str() {
Some(match s.to_lowercase().as_str() {
$(
$B64 => ($val, BitMode::B64),
$B32 => ($val, BitMode::B32),
$B16 => ($val, BitMode::B16),
$B8 => ($val, BitMode::B8),
$($B16H => ($val, BitMode::B16H),)?
stringify!($B64) => reg::$B64,
stringify!($B32) => reg::$B32,
stringify!($B16) => reg::$B16,
stringify!($B8 ) => reg::$B8,
$(
stringify!($B8H) => reg::$B8H,
)?
)*
_ => return None,
};
Some(RegMode {
reg: Reg(reg),
mode,
})
}
}
@@ -34,30 +122,148 @@ macro_rules! def_regs {
}
def_regs! {
0b0000 A : "rax" "eax" "ax" "al" "ah",
0b0001 C : "rcx" "ecx" "cx" "cl" "ch",
0b0010 D : "rdx" "edx" "dx" "dl" "dh",
0b0011 B : "rbx" "ebx" "bx" "bl" "bh",
0b0000 : rax eax ax al ah=spl,
0b0001 : rcx ecx cx cl ch=bpl,
0b0010 : rdx edx dx dl dh=sil,
0b0011 : rbx ebx bx bl bh=dil,
0b0100 SP: "rsp" "esp" "sp" "spl",
0b0101 BP: "rbp" "ebp" "bp" "sbl",
0b0110 SI: "rsi" "esi" "si" "sil",
0b0111 DI: "rdi" "edi" "di" "dil",
0b0100 : rsp esp sp spl,
0b0101 : rbp ebp bp bpl,
0b0110 : rsi esi si sil,
0b0111 : rdi edi di dil,
0b1000 R8 : "r8" "r8d" "r8w" "r8b",
0b1001 R9 : "r9" "r9d" "r9w" "r9b",
0b1010 R10: "r10" "r10d" "r10w" "r10b",
0b1011 R11: "r11" "r11d" "r11w" "r11b",
0b1100 R12: "r12" "r12d" "r12w" "r12b",
0b1101 R13: "r13" "r13d" "r13w" "r13b",
0b1110 R14: "r14" "r14d" "r14w" "r14b",
0b1111 R15: "r15" "r15d" "r15w" "r15b",
0b1000 : r8 r8d r8w r8b,
0b1001 : r9 r9d r9w r9b,
0b1010 : r10 r10d r10w r10b,
0b1011 : r11 r11d r11w r11b,
0b1100 : r12 r12d r12w r12b,
0b1101 : r13 r13d r13w r13b,
0b1110 : r14 r14d r14w r14b,
0b1111 : r15 r15d r15w r15b,
}
pub enum BitMode {
#[derive(Clone, Copy, PartialEq)]
pub enum BitWidth {
B64,
B32,
B16,
B16H,
B8,
}
impl BitWidth {
pub const fn max(&self) -> u64 {
match self {
Self::B64 => u64::MAX,
Self::B32 => u32::MAX as u64,
Self::B16 => u16::MAX as u64,
Self::B8 => u8::MAX as u64,
}
}
pub const fn bytes(&self) -> usize {
match self {
Self::B64 => 8,
Self::B32 => 4,
Self::B16 => 2,
Self::B8 => 1,
}
}
}
pub fn mov(dst: RegMode, src: impl Into<RegImm>) -> Instr {
Instr::Mov {
dst,
src: src.into(),
}
}
impl From<RegMode> for RegImm {
fn from(value: RegMode) -> Self {
Self::Reg(value)
}
}
impl From<u64> for RegImm {
fn from(value: u64) -> Self {
Self::Imm(value)
}
}
#[cfg(test)]
mod test {
use super::*;
use reg::*;
fn eq(expected: impl AsRef<[u8]>, got: Instr) {
let expected = expected.as_ref();
let mut res = Vec::new();
if let Err(e) = got.compile(&mut res) {
panic!("expected {expected:x?}, failed to compile: {}", e.msg);
}
assert_eq!(expected, &res[..], "expected {expected:x?}, got {res:x?}");
}
#[test]
fn reg_reg() {
// used objdump on some nasm compiled assembly
eq([0x48, 0x89, 0xd8], mov(rax, rbx));
eq([0x89, 0xd8], mov(eax, ebx));
eq([0x66, 0x89, 0xd8], mov(ax, bx));
eq([0x88, 0xd8], mov(al, bl));
eq([0x88, 0xfc], mov(ah, bh));
eq([0x88, 0xf8], mov(al, bh));
eq([0x88, 0xdc], mov(ah, bl));
eq([0x40, 0x88, 0xe7], mov(dil, spl));
eq([0x4d, 0x89, 0xc8], mov(r8, r9));
eq([0x45, 0x89, 0xc8], mov(r8d, r9d));
eq([0x66, 0x45, 0x89, 0xc8], mov(r8w, r9w));
eq([0x45, 0x88, 0xc8], mov(r8b, r9b));
eq([0x49, 0x89, 0xc0], mov(r8, rax));
eq([0x4c, 0x89, 0xc0], mov(rax, r8));
eq([0x4d, 0x89, 0xd1], mov(r9, r10));
eq([0x4d, 0x89, 0xe0], mov(r8, r12));
}
#[test]
fn reg_imm() {
eq(
[0x49, 0xbf, 0xf0, 0xde, 0xbc, 0x9a, 0x78, 0x56, 0x34, 0x12],
mov(r15, 0x123456789abcdef0),
);
eq(
[0x49, 0xb8, 0xf0, 0xde, 0xbc, 0x9a, 0x78, 0x56, 0x34, 0x12],
mov(r8, 0x123456789abcdef0),
);
eq(
[0x49, 0xb9, 0xf0, 0xde, 0xbc, 0x9a, 0x78, 0x56, 0x34, 0x12],
mov(r9, 0x123456789abcdef0),
);
eq([0x41, 0xb9, 0x78, 0x56, 0x34, 0x12], mov(r9d, 0x12345678));
eq([0x66, 0x41, 0xb9, 0x34, 0x12], mov(r9w, 0x1234));
eq([0x41, 0xb1, 0x12], mov(r9b, 0x12));
eq([0x41, 0xb0, 0x12], mov(r8b, 0x12));
eq([0x41, 0xb7, 0x12], mov(r15b, 0x12));
eq(
[0x48, 0xb8, 0xf0, 0xde, 0xbc, 0x9a, 0x78, 0x56, 0x34, 0x12],
mov(rax, 0x123456789abcdef0),
);
eq(
[0x48, 0xbb, 0xf0, 0xde, 0xbc, 0x9a, 0x78, 0x56, 0x34, 0x12],
mov(rbx, 0x123456789abcdef0),
);
eq(
[0x48, 0xbf, 0xf0, 0xde, 0xbc, 0x9a, 0x78, 0x56, 0x34, 0x12],
mov(rdi, 0x123456789abcdef0),
);
eq([0xbb, 0x78, 0x56, 0x34, 0x12], mov(ebx, 0x12345678));
eq([0x66, 0xbb, 0x34, 0x12], mov(bx, 0x1234));
eq([0xb3, 0x12], mov(bl, 0x12));
eq([0xb7, 0x12], mov(bh, 0x12));
eq([0xb4, 0x12], mov(ah, 0x12));
eq([0x40, 0xb7, 0x12], mov(dil, 0x12));
}
}