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iris
2026-06-17 00:22:10 -04:00
parent 113f3d4d9c
commit 026aec8565
2 changed files with 22 additions and 19 deletions
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src/arch/x86_64/encode.rs
+9 -13
View File
@@ -11,11 +11,10 @@ pub struct Code {
} }
impl Code { impl Code {
pub fn mov(&mut self, dst: impl Into<RegMem>, src: impl Into<RegImmMem>) -> ERes { pub fn mov(&mut self, dst: impl RegMem, src: impl Into<RegImmMem>) -> ERes {
let dst = dst.into();
let src = src.into(); let src = src.into();
match dst { match dst.kind() {
RegMem::Reg(mut dst) => match src { RegMemKind::Reg(mut dst) => match src {
RegImmMem::Reg(src) => { RegImmMem::Reg(src) => {
if dst.width() != src.width() { if dst.width() != src.width() {
return Err("src and dst are not same width".into()); return Err("src and dst are not same width".into());
@@ -62,7 +61,7 @@ impl Code {
self.modrm(dst, src); self.modrm(dst, src);
} }
}, },
RegMem::Mem(dst) => match src { RegMemKind::Mem(dst) => match src {
RegImmMem::Reg(src) => { RegImmMem::Reg(src) => {
if src.width() != dst.width { if src.width() != dst.width {
return Err("register & memory sizes don't match".into()); return Err("register & memory sizes don't match".into());
@@ -111,7 +110,7 @@ impl Code {
} }
self.bytes.push(0x50 | reg.base()); self.bytes.push(0x50 | reg.base());
} }
Width::B16 => {} Width::B16 => todo!(),
_ => return Err("register must be 64 or 16 bit".into()), _ => return Err("register must be 64 or 16 bit".into()),
}, },
RegImmMem::Imm(imm) => match imm.width_unsigned()? { RegImmMem::Imm(imm) => match imm.width_unsigned()? {
@@ -171,7 +170,7 @@ impl Code {
self.bytes.push(0xc3); self.bytes.push(0xc3);
} }
fn add_sub(&mut self, dst: impl RegMem_, src: impl Into<Imm>, ext: u8) -> ERes { fn add_sub(&mut self, dst: impl RegMem, src: impl Into<Imm>, ext: u8) -> ERes {
let mut src = src.into(); let mut src = src.into();
let mut imm_width = src.width_signed()?; let mut imm_width = src.width_signed()?;
let dst_width = dst.width().min(Width::B32); let dst_width = dst.width().min(Width::B32);
@@ -202,14 +201,11 @@ impl Code {
Ok(()) Ok(())
} }
pub fn add(&mut self, dst: impl Into<RegMem>, src: impl Into<Imm>) -> ERes { pub fn add(&mut self, dst: impl RegMem, src: impl Into<Imm>) -> ERes {
match dst.into() { self.add_sub(dst, src, 0)
RegMem::Reg(dst) => self.add_sub(dst, src, 0),
RegMem::Mem(dst) => self.add_sub(dst, src, 0),
}
} }
pub fn sub(&mut self, dst: Reg, src: impl Into<Imm>) -> ERes { pub fn sub(&mut self, dst: impl RegMem, src: impl Into<Imm>) -> ERes {
self.add_sub(dst, src, 5) self.add_sub(dst, src, 5)
} }
src/arch/x86_64/types/arg.rs
+13 -6
View File
@@ -9,23 +9,27 @@ pub enum RegImmMem {
} }
#[derive(Clone, Copy)] #[derive(Clone, Copy)]
pub enum RegMem { pub enum RegMemKind {
Reg(Reg), Reg(Reg),
Mem(Mem), Mem(Mem),
} }
pub trait RegMem_: RexBit + RexW + ModRMRM + Copy + MaybeMem { pub trait RegMem: RexBit + RexW + ModRMRM + Copy + MaybeMem {
fn width(&self) -> Width; fn width(&self) -> Width;
fn kind(self) -> RegMemKind;
} }
pub trait MaybeMem { pub trait MaybeMem {
fn mem(&self) -> Option<Mem>; fn mem(&self) -> Option<Mem>;
} }
impl RegMem_ for Reg { impl RegMem for Reg {
fn width(&self) -> Width { fn width(&self) -> Width {
self.width() self.width()
} }
fn kind(self) -> RegMemKind {
RegMemKind::Reg(self)
}
} }
impl MaybeMem for Reg { impl MaybeMem for Reg {
@@ -34,10 +38,13 @@ impl MaybeMem for Reg {
} }
} }
impl RegMem_ for Mem { impl RegMem for Mem {
fn width(&self) -> Width { fn width(&self) -> Width {
self.width self.width
} }
fn kind(self) -> RegMemKind {
RegMemKind::Mem(self)
}
} }
impl MaybeMem for Mem { impl MaybeMem for Mem {
@@ -53,7 +60,7 @@ impl From<Reg> for RegImmMem {
} }
} }
impl From<Reg> for RegMem { impl From<Reg> for RegMemKind {
fn from(value: Reg) -> Self { fn from(value: Reg) -> Self {
Self::Reg(value) Self::Reg(value)
} }
@@ -65,7 +72,7 @@ impl From<Mem> for RegImmMem {
} }
} }
impl From<Mem> for RegMem { impl From<Mem> for RegMemKind {
fn from(value: Mem) -> Self { fn from(value: Mem) -> Self {
Self::Mem(value) Self::Mem(value)
} }