From 026aec856533ce98a2eba47314a6ad78a556a060 Mon Sep 17 00:00:00 2001
From: Shadow Cat <shadowcatzero@protonmail.com>
Date: Wed, 17 Jun 2026 00:22:10 -0400
Subject: [PATCH] stuff

---
 src/arch/x86_64/encode.rs    | 22 +++++++++-------------
 src/arch/x86_64/types/arg.rs | 19 +++++++++++++------
 2 files changed, 22 insertions(+), 19 deletions(-)

diff --git a/src/arch/x86_64/encode.rs b/src/arch/x86_64/encode.rs
index 1ce1c97..482cedc 100644
--- a/src/arch/x86_64/encode.rs
+++ b/src/arch/x86_64/encode.rs
@@ -11,11 +11,10 @@ pub struct Code {
 }
 
 impl Code {
-    pub fn mov(&mut self, dst: impl Into<RegMem>, src: impl Into<RegImmMem>) -> ERes {
-        let dst = dst.into();
+    pub fn mov(&mut self, dst: impl RegMem, src: impl Into<RegImmMem>) -> ERes {
         let src = src.into();
-        match dst {
-            RegMem::Reg(mut dst) => match src {
+        match dst.kind() {
+            RegMemKind::Reg(mut dst) => match src {
                 RegImmMem::Reg(src) => {
                     if dst.width() != src.width() {
                         return Err("src and dst are not same width".into());
@@ -62,7 +61,7 @@ impl Code {
                     self.modrm(dst, src);
                 }
             },
-            RegMem::Mem(dst) => match src {
+            RegMemKind::Mem(dst) => match src {
                 RegImmMem::Reg(src) => {
                     if src.width() != dst.width {
                         return Err("register & memory sizes don't match".into());
@@ -111,7 +110,7 @@ impl Code {
                     }
                     self.bytes.push(0x50 | reg.base());
                 }
-                Width::B16 => {}
+                Width::B16 => todo!(),
                 _ => return Err("register must be 64 or 16 bit".into()),
             },
             RegImmMem::Imm(imm) => match imm.width_unsigned()? {
@@ -171,7 +170,7 @@ impl Code {
         self.bytes.push(0xc3);
     }
 
-    fn add_sub(&mut self, dst: impl RegMem_, src: impl Into<Imm>, ext: u8) -> ERes {
+    fn add_sub(&mut self, dst: impl RegMem, src: impl Into<Imm>, ext: u8) -> ERes {
         let mut src = src.into();
         let mut imm_width = src.width_signed()?;
         let dst_width = dst.width().min(Width::B32);
@@ -202,14 +201,11 @@ impl Code {
         Ok(())
     }
 
-    pub fn add(&mut self, dst: impl Into<RegMem>, src: impl Into<Imm>) -> ERes {
-        match dst.into() {
-            RegMem::Reg(dst) => self.add_sub(dst, src, 0),
-            RegMem::Mem(dst) => self.add_sub(dst, src, 0),
-        }
+    pub fn add(&mut self, dst: impl RegMem, src: impl Into<Imm>) -> ERes {
+        self.add_sub(dst, src, 0)
     }
 
-    pub fn sub(&mut self, dst: Reg, src: impl Into<Imm>) -> ERes {
+    pub fn sub(&mut self, dst: impl RegMem, src: impl Into<Imm>) -> ERes {
         self.add_sub(dst, src, 5)
     }
 
diff --git a/src/arch/x86_64/types/arg.rs b/src/arch/x86_64/types/arg.rs
index 24e2cef..a81eb42 100644
--- a/src/arch/x86_64/types/arg.rs
+++ b/src/arch/x86_64/types/arg.rs
@@ -9,23 +9,27 @@ pub enum RegImmMem {
 }
 
 #[derive(Clone, Copy)]
-pub enum RegMem {
+pub enum RegMemKind {
     Reg(Reg),
     Mem(Mem),
 }
 
-pub trait RegMem_: RexBit + RexW + ModRMRM + Copy + MaybeMem {
+pub trait RegMem: RexBit + RexW + ModRMRM + Copy + MaybeMem {
     fn width(&self) -> Width;
+    fn kind(self) -> RegMemKind;
 }
 
 pub trait MaybeMem {
     fn mem(&self) -> Option<Mem>;
 }
 
-impl RegMem_ for Reg {
+impl RegMem for Reg {
     fn width(&self) -> Width {
         self.width()
     }
+    fn kind(self) -> RegMemKind {
+        RegMemKind::Reg(self)
+    }
 }
 
 impl MaybeMem for Reg {
@@ -34,10 +38,13 @@ impl MaybeMem for Reg {
     }
 }
 
-impl RegMem_ for Mem {
+impl RegMem for Mem {
     fn width(&self) -> Width {
         self.width
     }
+    fn kind(self) -> RegMemKind {
+        RegMemKind::Mem(self)
+    }
 }
 
 impl MaybeMem for Mem {
@@ -53,7 +60,7 @@ impl From<Reg> for RegImmMem {
     }
 }
 
-impl From<Reg> for RegMem {
+impl From<Reg> for RegMemKind {
     fn from(value: Reg) -> Self {
         Self::Reg(value)
     }
@@ -65,7 +72,7 @@ impl From<Mem> for RegImmMem {
     }
 }
 
-impl From<Mem> for RegMem {
+impl From<Mem> for RegMemKind {
     fn from(value: Mem) -> Self {
         Self::Mem(value)
     }