made riscv init more sane

kernel/src/arch/riscv64/mod.rs

@@ -1,31 +1,45 @@
-use crate::main;
+use crate::{main, println};
 
 pub mod qemu;
 
 #[no_mangle]
 #[link_section = ".text.init"]
-pub extern "C" fn _start() -> ! {
+#[naked]
-    unsafe {
+unsafe extern "C" fn _start() -> ! {
-        core::arch::asm!(
+    core::arch::asm!(
-            "csrr    t0, mhartid",
+        ".option push",
-            "bnez    t0, {_start}",
+        ".option norelax",
-            _start = sym _start
+        "la gp, global_pointer",
-        );
+        "la sp, stack_top",
-        core::arch::asm!(
+        ".option pop",
-            ".option push",
-            ".option norelax",
 
-            "la gp, global_pointer",
+        "csrr a0, mhartid",
-            "la sp, stack_top",
+        "slli t0, a0, 12",
+        "sub sp, sp, t0",
+        "tail {entry}",
 
-            "tail {entry}",
+        entry = sym entry,
-            entry = sym entry,
+        options(noreturn)
-            options(noreturn)
+    );
-        );
-    }
 }
 
-extern "C" fn entry() -> ! {
+fn get_hartid() -> u64 {
+    let mut hart: u64;
+    unsafe {
+        core::arch::asm!(
+            "csrr {hart}, mhartid",
+            hart = out(reg) hart
+        );
+    }
+    return hart
+}
+
+fn entry() -> ! {
+    let hart = get_hartid();
+    println!("yo from hart {hart}");
+    if hart != 0 {
+        loop {}
+    }
     main()
 }
 

kernel/src/arch/riscv64/qemu.rs

@@ -1,5 +1,32 @@
-const UART_BASE: u32 = 0x10010000;
+use core::fmt::{self, Write};
-const UART_REG_TXFIFO: *mut i32 = (UART_BASE + 0) as *mut i32;
+
+use spin::Mutex;
+
+// --machine sifive_u
+// const UART_BASE: u32 = 0x10010000;
+// --machine virt
+const UART_BASE: u32 = 0x10000000;
+static UART: Mutex<Uart> = Mutex::new(Uart::new(UART_BASE));
+
+struct Uart {
+    base: u32,
+}
+
+impl Uart {
+    pub const fn new(base: u32) -> Self {
+        Self { base }
+    }
+}
+
+impl fmt::Write for Uart {
+    fn write_str(&mut self, s: &str) -> fmt::Result {
+        for b in s.as_bytes() {
+            while unsafe { *(self.base as *mut i32) } < 0 {}
+            unsafe { *(self.base as *mut i32) = *b as i32 }
+        }
+        Ok(())
+    }
+}
 
 pub fn exit() -> ! {
     unsafe {
@@ -20,9 +47,5 @@ pub fn exit() -> ! {
 }
 
 pub fn _print(args: core::fmt::Arguments<'_>) {
-    let msg = args.as_str().expect("bruh");
+    UART.lock().write_fmt(args).unwrap();
-    for b in msg.as_bytes() {
-        while unsafe { *UART_REG_TXFIFO } < 0 {}
-        unsafe { *UART_REG_TXFIFO = *b as i32 }
-    }
 }

kernel/src/lib2.rs

@@ -1,26 +0,0 @@
-#![no_std]
-#![feature(abi_x86_interrupt)]
-
-pub mod arch;
-pub mod log;
-pub mod qemu;
-
-pub fn main() -> ! {
-    println!("we out here vibin");
-    for _ in 0..20000000 {}
-    qemu::exit();
-}
-
-pub fn exit() -> ! {
-    qemu::exit();
-}
-
-pub fn hlt_loop() -> ! {
-    arch::hlt_loop();
-}
-
-#[panic_handler]
-pub fn panic(info: &core::panic::PanicInfo) -> ! {
-    println!("{}", info);
-    exit()
-}

kernel/src/main.rs

@@ -1,10 +1,12 @@
 #![no_std]
 #![no_main]
 #![feature(abi_x86_interrupt)]
+#![feature(naked_functions)]
 
 pub mod arch;
 pub mod log;
 pub mod qemu;
+pub mod sync;
 
 pub fn main() -> ! {
     println!("we out here vibin");

kernel/src/sync/mod.rs

@@ -0,0 +1,26 @@
+// use core::sync::atomic::AtomicBool;
+//
+// struct SpinLock(AtomicBool);
+//
+// impl SpinLock {
+//     pub fn new() -> Self {
+//         Self(AtomicBool::new(false))
+//     }
+//     pub fn lock(&mut self) {
+//         while self.0.swap(true, core::sync::atomic::Ordering::Acquire) {}
+//     }
+//     pub fn release(&mut self) {
+//         self.0.store(false, core::sync::atomic::Ordering::Release);
+//     }
+// }
+//
+// struct Mutex<T> {
+//     lock: SpinLock,
+//     data: T
+// }
+//
+// struct MutexGuard<T>(T);
+//
+// impl <T> MutexGuard<T> {
+// }
+//

runner/src/main.rs

@@ -38,12 +38,12 @@ fn run_qemu(target: &Target, gdb: Option<Option<u16>>) {
         let handle = std::thread::spawn(move || {
             qemu.stdin(Stdio::null());
             qemu.stdout(Stdio::null());
-            let exit_status = qemu.status().unwrap();
+            qemu.status().unwrap();
         });
         gdb.status().unwrap();
         handle.join().unwrap();
     } else {
-        let exit_status = qemu.status().unwrap();
+        qemu.status().unwrap();
         // process::exit(exit_status.code().unwrap_or(-1));
     }
 }

runner/src/target.rs

@@ -40,8 +40,9 @@ impl Target {
                 let mut cmd = Command::new("qemu-system-riscv64");
                 cmd.arg("-nographic");
                 cmd.arg("-semihosting");
-                cmd.args(["-machine", "sifive_u"]);
+                cmd.args(["-machine", "virt"]);
                 cmd.args(["-bios", "none"]);
+                cmd.args(["-smp", "4"]);
                 cmd.args(["-kernel", &self.qemu_bin_path()]);
                 cmd
             }