start of ir

src/compiler/mod.rs

@@ -10,7 +10,7 @@ mod program;
 mod riscv64;
 mod target;
 
-use program::*;
+pub use program::*;
 
 pub fn main() {
     use std::io::prelude::*;

src/compiler/program.rs

@@ -59,13 +59,13 @@ impl Deref for WritableSymbol {
     }
 }
 
-pub struct SymMap<I: Instr> {
+pub struct SymMap<I> {
     i: usize,
     ro_data: Vec<(Vec<u8>, Symbol)>,
     functions: Vec<(Vec<I>, Symbol)>,
 }
 
-impl<I: Instr> SymMap<I> {
+impl<I> SymMap<I> {
     pub fn new() -> Self {
         Self {
             i: 0,

src/compiler/riscv64/asm.rs

@@ -3,7 +3,13 @@ use crate::compiler::program::{Addr, Instr, SymTable, Symbol};
 use super::*;
 
 pub enum AsmInstruction {
+    Add(Reg, Reg, Reg),
     Addi(Reg, Reg, i32),
+    Andi(Reg, Reg, i32),
+    Slli(Reg, Reg, i32),
+    Srli(Reg, Reg, i32),
+    Sd(Reg, i32, Reg),
+    Mv(Reg, Reg),
     La(Reg, Symbol),
     Jal(Reg, i32),
     Call(Symbol),
@@ -16,7 +22,13 @@ pub enum AsmInstruction {
 impl Instr for AsmInstruction {
     fn push(&self, data: &mut Vec<u8>, sym_map: &SymTable, pos: Addr, missing: bool) -> Option<Symbol> {
         let last = match self {
+            Self::Add(dest, src1, src2) => add(*dest, *src1, *src2),
             Self::Addi(dest, src, imm) => addi(*dest, *src, BitsI32::new(*imm)),
+            Self::Andi(dest, src, imm) => andi(*dest, *src, BitsI32::new(*imm)),
+            Self::Slli(dest, src, imm) => slli(*dest, *src, BitsI32::new(*imm)),
+            Self::Srli(dest, src, imm) => srli(*dest, *src, BitsI32::new(*imm)),
+            Self::Sd(src, offset, base) => sd(*src, BitsI32::new(*offset), *base),
+            Self::Mv(dest, src) => addi(*dest, *src, BitsI32::new(0)),
             Self::La(dest, sym) => {
                 if let Some(addr) = sym_map.get(*sym) {
                     let offset = addr.val() as i32 - pos.val() as i32;

src/compiler/riscv64/base.rs

@@ -18,14 +18,14 @@ impl Instruction {
 pub type Funct3 = Bits32<2, 0>;
 
 pub const fn r_type(
-    funct7: u32,
+    funct7: Bits32<6, 0>,
     rs2: Reg,
     rs1: Reg,
     funct3: Bits32<2, 0>,
     rd: Reg,
     opcode: u32,
 ) -> I {
-    I((funct7 << 25)
+    I((funct7.val() << 25)
         + (rs2.val() << 20)
         + (rs1.val() << 15)
         + (funct3.val() << 12)

src/compiler/riscv64/single.rs

@@ -31,9 +31,21 @@ pub const fn sw(src: Reg, offset: BitsI32<11, 0>, base: Reg) -> I {
 pub const fn sd(src: Reg, offset: BitsI32<11, 0>, base: Reg) -> I {
     s_type(src, base, width::D, offset.to_u(), STORE)
 }
+pub const fn add(dest: Reg, src1: Reg, src2: Reg) -> I {
+    r_type(Bits32::new(0), src2, src1, ADD, dest, OP)
+}
 pub const fn addi(dest: Reg, src: Reg, imm: BitsI32<11, 0>) -> I {
     i_type(imm.to_u(), src, ADD, dest, IMM_OP)
 }
+pub const fn andi(dest: Reg, src: Reg, imm: BitsI32<11, 0>) -> I {
+    i_type(imm.to_u(), src, AND, dest, IMM_OP)
+}
+pub const fn slli(dest: Reg, src: Reg, imm: BitsI32<4, 0>) -> I {
+    i_type(Bits32::new(imm.to_u().val()), src, SLL, dest, IMM_OP)
+}
+pub const fn srli(dest: Reg, src: Reg, imm: BitsI32<4, 0>) -> I {
+    i_type(Bits32::new(imm.to_u().val()), src, SR, dest, IMM_OP)
+}
 pub const fn jal(dest: Reg, offset: BitsI32<20, 1>) -> I {
     j_type(offset.to_u(), dest, JAL)
 }