From a5a5f64c495f1ca362321cd388c9c09f7a04ee86 Mon Sep 17 00:00:00 2001 From: shadow cat Date: Sun, 23 Mar 2025 15:05:28 -0400 Subject: [PATCH] more asm refactor --- src/compiler/arch/riscv/asm.rs | 90 +++++++++++++++++++++-------- src/compiler/arch/riscv/compile.rs | 4 ++ src/ir/arch/riscv64.rs | 88 +--------------------------- src/parser/v3/lower/arch/riscv64.rs | 16 ++--- 4 files changed, 80 insertions(+), 118 deletions(-) diff --git a/src/compiler/arch/riscv/asm.rs b/src/compiler/arch/riscv/asm.rs index ecc8086..91dfb1f 100644 --- a/src/compiler/arch/riscv/asm.rs +++ b/src/compiler/arch/riscv/asm.rs @@ -5,59 +5,59 @@ use crate::{ use super::*; -#[derive(Debug, Clone)] -pub enum LinkerInstruction { +#[derive(Clone, Copy)] +pub enum LinkerInstruction { Op { op: Funct3, funct: Funct7, - dest: Reg, - src1: Reg, - src2: Reg, + dest: R, + src1: R, + src2: R, }, OpImm { op: Funct3, - dest: Reg, - src: Reg, + dest: R, + src: R, imm: i32, }, OpImmF7 { op: Funct3, funct: Funct7, - dest: Reg, - src: Reg, + dest: R, + src: R, imm: i32, }, Store { width: Funct3, - src: Reg, + src: R, offset: i32, - base: Reg, + base: R, }, Load { width: Funct3, - dest: Reg, + dest: R, offset: i32, - base: Reg, + base: R, }, Mv { - dest: Reg, - src: Reg, + dest: R, + src: R, }, La { - dest: Reg, - src: Symbol, + dest: R, + src: S, }, Jal { - dest: Reg, + dest: R, offset: i32, }, - Call(Symbol), - J(Symbol), + Call(S), + J(S), Ret, Ecall, Li { - dest: Reg, - imm: i64, + dest: R, + imm: i32, }, } @@ -133,7 +133,7 @@ impl Instr for LinkerInstruction { } Self::Ret => ret(), Self::Ecall => ecall(), - Self::Li { dest, imm } => addi(*dest, zero, BitsI32::new(*imm as i32)), + Self::Li { dest, imm } => addi(*dest, zero, BitsI32::new(*imm)), }; data.extend(last.to_le_bytes()); None @@ -166,3 +166,47 @@ impl LinkerInstruction { } } } + +impl std::fmt::Debug for LinkerInstruction { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + match self { + Self::Ecall => write!(f, "ecall"), + Self::Li { dest, imm } => write!(f, "li {dest:?}, {imm:?}"), + Self::Mv { dest, src } => write!(f, "mv {dest:?}, {src:?}"), + Self::La { dest, src } => write!(f, "la {dest:?}, {src:?}"), + Self::Load { + width, + dest, + offset, + base, + } => write!(f, "l{} {dest:?}, {offset}({base:?})", width::str(*width)), + Self::Store { + width, + src, + offset, + base, + } => write!(f, "s{} {src:?}, {offset}({base:?})", width::str(*width)), + Self::Op { + op, + funct, + dest, + src1, + src2, + } => write!(f, "{} {dest:?}, {src1:?}, {src2:?}", opstr(*op, *funct)), + Self::OpImm { op, dest, src, imm } => { + write!(f, "{}i {dest:?}, {src:?}, {imm}", opstr(*op, op32i::FUNCT7)) + } + Self::OpImmF7 { + op, + funct, + dest, + src, + imm, + } => write!(f, "{}i {dest:?}, {src:?}, {imm}", opstr(*op, *funct)), + Self::Jal { dest, offset } => write!(f, "jal {dest:?}, {offset:?}"), + Self::Call(s) => write!(f, "call {s:?}"), + Self::J(s) => write!(f, "j {s:?}"), + Self::Ret => write!(f, "ret"), + } + } +} diff --git a/src/compiler/arch/riscv/compile.rs b/src/compiler/arch/riscv/compile.rs index 7c981eb..ce8ec80 100644 --- a/src/compiler/arch/riscv/compile.rs +++ b/src/compiler/arch/riscv/compile.rs @@ -195,6 +195,10 @@ pub fn compile(program: IRLProgram) -> (Vec, Option) { src: r(src), imm: imm as i32, }), + AI::Ret => v.push(LI::Ret), + AI::Call(s) => todo!(), + AI::Jal { dest, offset } => todo!(), + AI::J(s) => todo!(), } } } diff --git a/src/ir/arch/riscv64.rs b/src/ir/arch/riscv64.rs index 39ec2bf..90f322e 100644 --- a/src/ir/arch/riscv64.rs +++ b/src/ir/arch/riscv64.rs @@ -1,53 +1,6 @@ use crate::{compiler::arch::riscv::*, ir::VarInst}; -#[derive(Copy, Clone)] -pub enum RV64Instruction { - Ecall, - Li { - dest: RegRef, - imm: i64, - }, - Mv { - dest: RegRef, - src: RegRef, - }, - La { - dest: RegRef, - src: VarInst, - }, - Load { - width: Funct3, - dest: RegRef, - offset: i64, - base: RegRef, - }, - Store { - width: Funct3, - src: RegRef, - offset: i64, - base: RegRef, - }, - Op { - op: Funct3, - funct: Funct7, - dest: RegRef, - src1: RegRef, - src2: RegRef, - }, - OpImm { - op: Funct3, - dest: RegRef, - src: RegRef, - imm: i64, - }, - OpImmF7 { - op: Funct3, - funct: Funct7, - dest: RegRef, - src: RegRef, - imm: i64, - }, -} +pub type RV64Instruction = LinkerInstruction; #[derive(Copy, Clone)] pub enum RegRef { @@ -64,42 +17,3 @@ impl std::fmt::Debug for RegRef { } } -impl std::fmt::Debug for RV64Instruction { - fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { - match self { - Self::Ecall => write!(f, "ecall"), - Self::Li { dest, imm } => write!(f, "li {dest:?}, {imm:?}"), - Self::Mv { dest, src } => write!(f, "mv {dest:?}, {src:?}"), - Self::La { dest, src } => write!(f, "la {dest:?}, {src:?}"), - Self::Load { - width, - dest, - offset, - base, - } => write!(f, "l{} {dest:?}, {offset}({base:?})", width::str(*width)), - Self::Store { - width, - src, - offset, - base, - } => write!(f, "s{} {src:?}, {offset}({base:?})", width::str(*width)), - Self::Op { - op, - funct, - dest, - src1, - src2, - } => write!(f, "{} {dest:?}, {src1:?}, {src2:?}", opstr(*op, *funct)), - Self::OpImm { op, dest, src, imm } => { - write!(f, "{}i {dest:?}, {src:?}, {imm}", opstr(*op, op32i::FUNCT7)) - } - Self::OpImmF7 { - op, - funct, - dest, - src, - imm, - } => write!(f, "{}i {dest:?}, {src:?}, {imm}", opstr(*op, *funct)), - } - } -} diff --git a/src/parser/v3/lower/arch/riscv64.rs b/src/parser/v3/lower/arch/riscv64.rs index bbe18e6..2407d31 100644 --- a/src/parser/v3/lower/arch/riscv64.rs +++ b/src/parser/v3/lower/arch/riscv64.rs @@ -18,7 +18,7 @@ impl RV64Instruction { }; let dest = RegRef::from_arg(dest, ctx)?; let src = RegRef::from_arg(src, ctx)?; - let imm = i64_from_arg(imm, ctx)?; + let imm = i32_from_arg(imm, ctx)?; Some(Self::OpImm { op, dest, src, imm }) }; let op = |ctx: &mut FnLowerCtx<'_, '_>, op: Funct3, funct: Funct7| -> Option { @@ -44,7 +44,7 @@ impl RV64Instruction { }; let dest = RegRef::from_arg(dest, ctx)?; let src = RegRef::from_arg(src, ctx)?; - let imm = i64_from_arg(imm, ctx)?; + let imm = i32_from_arg(imm, ctx)?; Some(Self::OpImmF7 { op, funct, @@ -59,7 +59,7 @@ impl RV64Instruction { return None; }; let src = RegRef::from_arg(src, ctx)?; - let offset = i64_from_arg(offset, ctx)?; + let offset = i32_from_arg(offset, ctx)?; let base = RegRef::from_arg(base, ctx)?; Some(Self::Store { width, @@ -74,7 +74,7 @@ impl RV64Instruction { return None; }; let dest = RegRef::from_arg(dest, ctx)?; - let offset = i64_from_arg(offset, ctx)?; + let offset = i32_from_arg(offset, ctx)?; let base = RegRef::from_arg(base, ctx)?; Some(Self::Load { width, @@ -91,7 +91,7 @@ impl RV64Instruction { return None; }; let dest = RegRef::from_arg(dest, ctx)?; - let imm = i64_from_arg(imm, ctx)?; + let imm = i32_from_arg(imm, ctx)?; Self::Li { dest, imm } } "la" => { @@ -199,13 +199,13 @@ impl Reg { } } -fn i64_from_arg(node: &Node, ctx: &mut FnLowerCtx) -> Option { +fn i32_from_arg(node: &Node, ctx: &mut FnLowerCtx) -> Option { let PAsmArg::Value(node) = node.inner.as_ref()? else { - ctx.err_at(node.span, "Expected an i64, found reference".to_string()); + ctx.err_at(node.span, "Expected an i32, found reference".to_string()); return None; }; let word = node.inner.as_ref()?; - match word.parse::() { + match word.parse::() { Ok(x) => Some(x), Err(_) => { ctx.err_at(node.span, format!("Expected an i64, found {}", word));