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actually compiles and does stuff now

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This commit is contained in:
shadow cat
2024-12-06 19:44:33 -05:00
parent 31c197e991
commit 620c4557e9
67 changed files with 1931 additions and 1287 deletions
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3
src/compiler/arch/mod.rs Normal file
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@@ -0,0 +1,3 @@
pub mod riscv64;
use super::*;

22
src/compiler/riscv64/asm.rs → src/compiler/arch/riscv64/asm.rs
View File

@@ -1,33 +1,34 @@
use crate::compiler::program::{Addr, Instr, SymTable, Symbol};
use crate::{compiler::program::{Addr, Instr, SymTable}, ir::AddrID};
use super::*;
#[derive(Debug, Clone)]
pub enum AsmInstruction {
pub enum LinkerInstruction {
Add { dest: Reg, src1: Reg, src2: Reg },
Addi { dest: Reg, src: Reg, imm: i32 },
Andi { dest: Reg, src: Reg, imm: i32 },
Slli { dest: Reg, src: Reg, imm: i32 },
Srli { dest: Reg, src: Reg, imm: i32 },
Sd { src: Reg, offset: i32, base: Reg },
Ld { dest: Reg, offset: i32, base: Reg },
Mv { dest: Reg, src: Reg },
La { dest: Reg, sym: Symbol },
La { dest: Reg, src: AddrID },
Jal { dest: Reg, offset: i32 },
Call(Symbol),
J(Symbol),
Call(AddrID),
J(AddrID),
Ret,
Ecall,
Li { dest: Reg, imm: i64 },
}
impl Instr for AsmInstruction {
impl Instr for LinkerInstruction {
fn push(
&self,
data: &mut Vec<u8>,
sym_map: &SymTable,
pos: Addr,
missing: bool,
) -> Option<Symbol> {
) -> Option<AddrID> {
let last = match self {
Self::Add { dest, src1, src2 } => add(*dest, *src1, *src2),
Self::Addi { dest, src, imm } => addi(*dest, *src, BitsI32::new(*imm)),
@@ -35,15 +36,16 @@ impl Instr for AsmInstruction {
Self::Slli { dest, src, imm } => slli(*dest, *src, BitsI32::new(*imm)),
Self::Srli { dest, src, imm } => srli(*dest, *src, BitsI32::new(*imm)),
Self::Sd { src, offset, base } => sd(*src, BitsI32::new(*offset), *base),
Self::Ld { dest, offset, base } => ld(*dest, BitsI32::new(*offset), *base),
Self::Mv { dest, src } => addi(*dest, *src, BitsI32::new(0)),
Self::La { dest, sym } => {
if let Some(addr) = sym_map.get(*sym) {
Self::La { dest, src } => {
if let Some(addr) = sym_map.get(*src) {
let offset = addr.val() as i32 - pos.val() as i32;
data.extend(auipc(*dest, BitsI32::new(0)).to_le_bytes());
addi(*dest, *dest, BitsI32::new(offset))
} else {
data.extend_from_slice(&[0; 2 * 4]);
return Some(*sym);
return Some(*src);
}
}
Self::Jal { dest, offset } => jal(*dest, BitsI32::new(*offset)),

6
src/compiler/riscv64/base.rs → src/compiler/arch/riscv64/base.rs
View File

@@ -2,11 +2,11 @@ use crate::util::Bits32;
use super::Reg;
pub struct Instruction(u32);
pub struct RawInstruction(u32);
use Instruction as I;
use RawInstruction as I;
impl Instruction {
impl RawInstruction {
pub fn to_le_bytes(&self) -> impl IntoIterator<Item = u8> {
self.0.to_le_bytes().into_iter()
}

117
src/compiler/arch/riscv64/compile.rs Normal file
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@@ -0,0 +1,117 @@
use std::collections::HashMap;
use crate::{
compiler::{arch::riscv64::Reg, create_program, Addr},
ir::{
arch::riscv64::{RV64Instruction as AI, RegRef},
IRLInstruction as IRI, Program,
},
};
use super::{LinkerInstruction as LI, *};
pub fn compile(program: Program) -> (Vec<u8>, Option<Addr>) {
let mut fns = Vec::new();
let mut data = Vec::new();
for d in program.data {
data.push((d.data, d.addr));
}
let mut start = None;
for f in program.fns {
let mut v = Vec::new();
let mut stack = HashMap::new();
let mut stack_len = 0;
if !f.stack.is_empty() || !f.args.is_empty() {
for (id, s) in &f.stack {
stack.insert(id, stack_len);
stack_len += *s as i32;
}
for (id, s) in f.args.iter().rev() {
stack.insert(id, stack_len);
stack_len += *s as i32;
}
v.push(LI::Addi {
dest: sp,
src: sp,
imm: -stack_len,
});
}
for i in &f.instructions {
match i {
IRI::Mv { dest, src } => todo!(),
IRI::Ref { dest, src } => todo!(),
IRI::LoadAddr { dest, src } => {
v.extend([
LI::La {
dest: t0,
src: *src,
},
LI::Sd {
src: t0,
offset: stack[dest],
base: sp,
},
]);
}
IRI::Call { dest, f, args } => {
let mut offset = 0;
for (arg, s) in args {
offset -= *s as i32;
v.extend([
LI::Ld {
dest: t0,
offset: stack[arg],
base: sp,
},
LI::Sd {
src: t0,
offset,
base: sp,
},
]);
}
v.push(LI::Call(*f));
}
IRI::AsmBlock { args, instructions } => {
for (reg, var) in args {
v.push(LI::Ld {
dest: *reg,
offset: stack[var],
base: sp,
});
}
fn r(rr: RegRef) -> Reg {
match rr {
RegRef::Var(var_ident) => todo!(),
RegRef::Reg(reg) => reg,
}
}
for i in instructions {
match *i {
AI::Ecall => v.push(LI::Ecall),
AI::Li { dest, imm } => v.push(LI::Li { dest: r(dest), imm }),
AI::Mv { dest, src } => v.push(LI::Mv {
dest: r(dest),
src: r(src),
}),
AI::La { dest, src } => todo!(),
AI::Ld { dest, base, offset } => v.push(LI::Ld {
dest: r(dest),
offset: offset as i32,
base: r(base),
}),
}
}
}
IRI::Ret { src } => todo!(),
}
}
if f.name == "start" {
start = Some(f.addr);
} else {
v.push(LI::Ret);
}
fns.push((v, f.addr));
}
create_program(fns, data, start)
}

0
src/compiler/riscv64/funct.rs → src/compiler/arch/riscv64/funct.rs
View File

63
src/compiler/arch/riscv64/mod.rs Normal file
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@@ -0,0 +1,63 @@
mod asm;
mod base;
mod funct;
mod opcode;
mod reg;
mod single;
mod compile;
use crate::util::BitsI32;
pub use asm::*;
use base::*;
use funct::{op::*, width};
use opcode::*;
pub use reg::*;
pub use compile::*;
use single::*;
pub fn gen() -> Vec<u8> {
// use asm::LinkerInstruction as I;
// let mut table = SymMap::new();
// let (msg, len) = table.push_ro_data_size(b"Hello world!\n".to_vec());
// let (msg2, len2) = table.push_ro_data_size(b"IT WORKS!!!!\n".to_vec());
// let print_stuff = table.reserve();
// let start = table.push_fn(vec![
// I::Call(*print_stuff),
// I::Li { dest: a0, imm: 0 },
// I::Li { dest: a7, imm: 93 },
// I::Ecall,
// I::Jal {
// dest: zero,
// offset: 0,
// },
// ]);
// table.write_fn(
// print_stuff,
// vec![
// I::Li { dest: a0, imm: 1 },
// I::La { dest: a1, src: msg },
// I::Li {
// dest: a2,
// imm: len as i64,
// },
// I::Li { dest: a7, imm: 64 },
// I::Ecall,
// I::Li { dest: a0, imm: 1 },
// I::La {
// dest: a1,
// src: msg2,
// },
// I::Li {
// dest: a2,
// imm: len2 as i64,
// },
// I::Li { dest: a7, imm: 64 },
// I::Ecall,
// I::Ret,
// ],
// );
// let (program, start) = create_program(table, Some(start));
// elf::create(program, start.expect("no start!"))
todo!("remove this");
}

0
src/compiler/riscv64/opcode.rs → src/compiler/arch/riscv64/opcode.rs
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179
src/compiler/arch/riscv64/reg.rs Normal file
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@@ -0,0 +1,179 @@
#![allow(non_upper_case_globals)]
#[derive(Clone, Copy)]
pub struct Reg(u8);
/// hard wired 0
pub const zero: Reg = Reg(0);
/// return address
pub const ra: Reg = Reg(1);
/// stack pointer
pub const sp: Reg = Reg(2);
/// global pointer
pub const gp: Reg = Reg(3);
/// thread pointer
pub const tp: Reg = Reg(4);
/// temp / alternate link
pub const t0: Reg = Reg(5);
pub const t1: Reg = Reg(6);
pub const t2: Reg = Reg(7);
pub const fp: Reg = Reg(8);
pub const s0: Reg = Reg(8);
pub const s1: Reg = Reg(9);
pub const a0: Reg = Reg(10);
pub const a1: Reg = Reg(11);
pub const a2: Reg = Reg(12);
pub const a3: Reg = Reg(13);
pub const a4: Reg = Reg(14);
pub const a5: Reg = Reg(15);
pub const a6: Reg = Reg(16);
pub const a7: Reg = Reg(17);
pub const s2: Reg = Reg(18);
pub const s3: Reg = Reg(19);
pub const s4: Reg = Reg(20);
pub const s5: Reg = Reg(21);
pub const s6: Reg = Reg(22);
pub const s7: Reg = Reg(23);
pub const s8: Reg = Reg(24);
pub const s9: Reg = Reg(25);
pub const s10: Reg = Reg(26);
pub const s11: Reg = Reg(27);
pub const t3: Reg = Reg(28);
pub const t4: Reg = Reg(29);
pub const t5: Reg = Reg(30);
pub const t6: Reg = Reg(31);
// pub const ft0: Reg = Reg(0);
// pub const ft1: Reg = Reg(1);
// pub const ft2: Reg = Reg(2);
// pub const ft3: Reg = Reg(3);
// pub const ft4: Reg = Reg(4);
// pub const ft5: Reg = Reg(5);
// pub const ft6: Reg = Reg(6);
// pub const ft7: Reg = Reg(7);
//
// pub const fs0: Reg = Reg(8);
// pub const fs1: Reg = Reg(9);
//
// pub const fa0: Reg = Reg(10);
// pub const fa1: Reg = Reg(11);
// pub const fa2: Reg = Reg(12);
// pub const fa3: Reg = Reg(13);
// pub const fa4: Reg = Reg(14);
// pub const fa5: Reg = Reg(15);
// pub const fa6: Reg = Reg(16);
// pub const fa7: Reg = Reg(17);
//
// pub const fs2: Reg = Reg(18);
// pub const fs3: Reg = Reg(19);
// pub const fs4: Reg = Reg(20);
// pub const fs5: Reg = Reg(21);
// pub const fs6: Reg = Reg(22);
// pub const fs7: Reg = Reg(23);
// pub const fs8: Reg = Reg(24);
// pub const fs9: Reg = Reg(25);
// pub const fs10: Reg = Reg(26);
// pub const fs11: Reg = Reg(27);
//
// pub const ft8: Reg = Reg(28);
// pub const ft9: Reg = Reg(29);
// pub const ft10: Reg = Reg(30);
// pub const ft11: Reg = Reg(31);
impl Reg {
#[inline]
pub const fn val(&self) -> u32 {
self.0 as u32
}
}
impl Reg {
pub fn from_str(str: &str) -> Option<Self> {
Some(match str {
"zero" => zero,
"ra" => ra,
"sp" => sp,
"gp" => gp,
"tp" => tp,
"t0" => t0,
"t1" => t1,
"t2" => t2,
"fp" => fp,
"s0" => s0,
"s1" => s1,
"a0" => a0,
"a1" => a1,
"a2" => a2,
"a3" => a3,
"a4" => a4,
"a5" => a5,
"a6" => a6,
"a7" => a7,
"s2" => s2,
"s3" => s3,
"s4" => s4,
"s5" => s5,
"s6" => s6,
"s7" => s7,
"s8" => s8,
"s9" => s9,
"s10" => s10,
"s11" => s11,
"t3" => t3,
"t4" => t4,
"t5" => t5,
"t6" => t6,
_ => {
return None;
}
})
}
}
impl std::fmt::Debug for Reg {
fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result {
write!(
f,
"{}",
match self.0 {
0 => "zero",
1 => "ra",
2 => "sp",
3 => "gp",
4 => "tp",
5 => "t0",
6 => "t1",
7 => "t2",
8 => "fp",
9 => "s1",
10 => "a0",
11 => "a1",
12 => "a2",
13 => "a3",
14 => "a4",
15 => "a5",
16 => "a6",
17 => "a7",
18 => "s2",
19 => "s3",
20 => "s4",
21 => "s5",
22 => "s6",
23 => "s7",
24 => "s8",
25 => "s9",
26 => "s10",
27 => "s11",
28 => "t3",
29 => "t4",
30 => "t5",
31 => "t6",
_ => "unknown",
}
)
}
}

2
src/compiler/riscv64/single.rs → src/compiler/arch/riscv64/single.rs
View File

@@ -2,7 +2,7 @@ use crate::util::{Bits32, BitsI32};
use super::*;
use Instruction as I;
use RawInstruction as I;
pub const fn ecall() -> I {
i_type(Bits32::new(0), zero, Bits32::new(0), zero, SYSTEM)

2
src/compiler/instruction.rs
View File

@@ -1,2 +0,0 @@
pub enum Instruction {
}

14
src/compiler/mod.rs
View File

@@ -5,14 +5,21 @@ use std::{
process::Command,
};
pub mod arch;
mod elf;
mod program;
pub mod riscv64;
mod target;
mod instruction;
pub use program::*;
use crate::ir::Program;
pub fn compile(program: Program) -> Vec<u8> {
let (compiled, start) = arch::riscv64::compile(program);
let binary = elf::create(compiled, start.expect("no start method found"));
binary
}
pub fn main() {
use std::io::prelude::*;
let dir = Path::new("./build");
@@ -27,7 +34,7 @@ pub fn main() {
.mode(0o750)
.open(path)
.expect("Failed to create file");
file.write_all(&riscv64::gen())
file.write_all(&arch::riscv64::gen())
.expect("Failed to write to file");
file.sync_all().expect("Failed to sync file");
let mut p = Command::new("qemu-riscv64");
@@ -64,4 +71,3 @@ pub fn main() {
}
}
}

43
src/compiler/program.rs
View File

@@ -1,14 +1,21 @@
use std::{collections::HashMap, ops::Deref};
pub fn create_program<I: Instr>(map: SymMap<I>, start: Symbol) -> (Vec<u8>, Option<Addr>) {
use crate::ir::AddrID;
pub fn create_program<I: Instr>(
fns: Vec<(Vec<I>, AddrID)>,
ro_data: Vec<(Vec<u8>, AddrID)>,
start: Option<AddrID>,
) -> (Vec<u8>, Option<Addr>) {
let mut data = Vec::new();
let mut sym_table = SymTable::new(map.len());
let mut missing = HashMap::<Symbol, Vec<(Addr, I)>>::new();
for (val, id) in map.ro_data {
let mut sym_table = SymTable::new(fns.len() + ro_data.len());
let mut missing = HashMap::<AddrID, Vec<(Addr, I)>>::new();
for (val, id) in ro_data {
sym_table.insert(id, Addr(data.len() as u64));
data.extend(val);
}
for (fun, id) in map.functions {
data.resize(data.len() + (4 - data.len() % 4), 0);
for (fun, id) in fns {
sym_table.insert(id, Addr(data.len() as u64));
for i in fun {
let i_pos = Addr(data.len() as u64);
@@ -30,11 +37,15 @@ pub fn create_program<I: Instr>(map: SymMap<I>, start: Symbol) -> (Vec<u8>, Opti
}
}
assert!(missing.is_empty());
(data, sym_table.get(start))
(
data,
start.map(|s| sym_table.get(s).expect("start symbol doesn't exist")),
)
}
pub trait Instr {
fn push(&self, data: &mut Vec<u8>, syms: &SymTable, pos: Addr, missing: bool) -> Option<Symbol>;
fn push(&self, data: &mut Vec<u8>, syms: &SymTable, pos: Addr, missing: bool)
-> Option<AddrID>;
}
#[derive(Debug, Clone, Copy, PartialEq)]
@@ -73,19 +84,23 @@ impl<I> SymMap<I> {
functions: Vec::new(),
}
}
pub fn push_ro_data(&mut self, data: impl Into<Vec<u8>>) -> (Symbol, usize) {
pub fn push_ro_data(&mut self, data: Vec<u8>) -> Symbol {
let sym = self.reserve();
self.write_ro_data(sym, data)
self.write_ro_data(sym, data.into())
}
pub fn push_ro_data_size(&mut self, data: Vec<u8>) -> (Symbol, usize) {
let sym = self.reserve();
let len = data.len();
(self.write_ro_data(sym, data), len)
}
pub fn push_fn(&mut self, instructions: Vec<I>) -> Symbol {
let sym = self.reserve();
self.write_fn(sym, instructions)
}
pub fn write_ro_data(&mut self, sym: WritableSymbol, data: impl Into<Vec<u8>>) -> (Symbol, usize) {
pub fn write_ro_data(&mut self, sym: WritableSymbol, data: Vec<u8>) -> Symbol {
let data = data.into();
let len = data.len();
self.ro_data.push((data, *sym));
(*sym, len)
*sym
}
pub fn write_fn(&mut self, sym: WritableSymbol, instructions: Vec<I>) -> Symbol {
self.functions.push((instructions, *sym));
@@ -106,10 +121,10 @@ impl SymTable {
pub fn new(len: usize) -> Self {
Self(vec![Addr::NONE; len])
}
pub fn insert(&mut self, sym: Symbol, addr: Addr) {
pub fn insert(&mut self, sym: AddrID, addr: Addr) {
self.0[sym.0] = addr;
}
pub fn get(&self, sym: Symbol) -> Option<Addr> {
pub fn get(&self, sym: AddrID) -> Option<Addr> {
match self.0[sym.0] {
Addr::NONE => None,
addr => Some(addr),

63
src/compiler/riscv64/mod.rs
View File

@@ -1,63 +0,0 @@
mod asm;
mod base;
mod funct;
mod opcode;
mod parse;
mod reg;
mod single;
use super::{create_program, elf, SymMap};
use crate::util::BitsI32;
pub use asm::*;
use base::*;
use funct::{op::*, width};
use opcode::*;
pub use parse::*;
pub use reg::*;
use single::*;
pub fn gen() -> Vec<u8> {
use asm::AsmInstruction as I;
let mut table = SymMap::new();
let (msg, len) = table.push_ro_data(b"Hello world!\n");
let (msg2, len2) = table.push_ro_data(b"IT WORKS!!!!\n");
let print_stuff = table.reserve();
let start = table.push_fn(vec![
I::Call(*print_stuff),
I::Li { dest: a0, imm: 0 },
I::Li { dest: a7, imm: 93 },
I::Ecall,
I::Jal {
dest: zero,
offset: 0,
},
]);
table.write_fn(
print_stuff,
vec![
I::Li { dest: a0, imm: 1 },
I::La { dest: a1, sym: msg },
I::Li {
dest: a2,
imm: len as i64,
},
I::Li { dest: a7, imm: 64 },
I::Ecall,
I::Li { dest: a0, imm: 1 },
I::La {
dest: a1,
sym: msg2,
},
I::Li {
dest: a2,
imm: len2 as i64,
},
I::Li { dest: a7, imm: 64 },
I::Ecall,
I::Ret,
],
);
let (program, start) = create_program(table, start);
elf::create(program, start.expect("no start!"))
}

104
src/compiler/riscv64/parse.rs
View File

@@ -1,104 +0,0 @@
use super::{reg::*, AsmInstruction, Reg};
use crate::parser::{Parsable, ParseResult, ParserMsg, ParserOutput, Symbol, Token};
impl Parsable for AsmInstruction {
fn parse(
cursor: &mut crate::parser::TokenCursor,
output: &mut ParserOutput,
) -> ParseResult<Self> {
let t = cursor.expect_next()?;
let span = t.span;
match &t.token {
Token::Word(w) => ParseResult::Ok(match w.as_str() {
"ecall" => Self::Ecall,
"li" => {
let dest = Reg::parse(cursor, output)?;
cursor.expect_sym(Symbol::Comma)?;
let imm = i64::parse(cursor, output)?;
Self::Li { dest, imm }
}
_ => {
return ParseResult::Err(ParserMsg::from_span(
span,
format!("Unknown instruction {}", w),
))
}
}),
_ => return ParseResult::Err(ParserMsg::unexpected_token(&t, "assembly or }")),
}
}
}
impl Parsable for Reg {
fn parse(
cursor: &mut crate::parser::TokenCursor,
output: &mut ParserOutput,
) -> ParseResult<Self> {
let next = cursor.expect_next()?;
let Token::Word(word) = next.token else {
return ParseResult::Err(ParserMsg::unexpected_token(&next, "a riscv register"));
};
ParseResult::Ok(match word.as_str() {
"zero" => zero,
"ra" => ra,
"sp" => sp,
"gp" => gp,
"tp" => tp,
"t0" => t0,
"t1" => t1,
"t2" => t2,
"fp" => fp,
"s0" => s0,
"s1" => s1,
"a0" => a0,
"a1" => a1,
"a2" => a2,
"a3" => a3,
"a4" => a4,
"a5" => a5,
"a6" => a6,
"a7" => a7,
"s2" => s2,
"s3" => s3,
"s4" => s4,
"s5" => s5,
"s6" => s6,
"s7" => s7,
"s8" => s8,
"s9" => s9,
"s10" => s10,
"s11" => s11,
"t3" => t3,
"t4" => t4,
"t5" => t5,
"t6" => t6,
other => {
return ParseResult::Err(ParserMsg::from_span(
next.span,
format!("Unknown reg name {}", other),
));
}
})
}
}
impl Parsable for i64 {
fn parse(
cursor: &mut crate::parser::TokenCursor,
_output: &mut ParserOutput,
) -> ParseResult<Self> {
let next = cursor.expect_next()?;
let span = next.span;
let Token::Word(word) = next.token else {
return ParseResult::Err(ParserMsg::unexpected_token(&next, "an i32"));
};
let res = word.parse::<Self>();
match res {
Ok(int) => ParseResult::Ok(int),
Err(_) => ParseResult::Err(ParserMsg::from_span(
span,
format!("Expected an i32, found {}", word),
)),
}
}
}

94
src/compiler/riscv64/reg.rs
View File

@@ -1,94 +0,0 @@
#![allow(non_upper_case_globals)]
#[derive(Debug, Clone, Copy)]
pub struct Reg(u8);
/// hard wired 0
pub const zero: Reg = Reg(0);
/// return address
pub const ra: Reg = Reg(1);
/// stack pointer
pub const sp: Reg = Reg(2);
/// global pointer
pub const gp: Reg = Reg(3);
/// thread pointer
pub const tp: Reg = Reg(4);
/// temp / alternate link
pub const t0: Reg = Reg(5);
pub const t1: Reg = Reg(6);
pub const t2: Reg = Reg(7);
pub const fp: Reg = Reg(8);
pub const s0: Reg = Reg(8);
pub const s1: Reg = Reg(9);
pub const a0: Reg = Reg(10);
pub const a1: Reg = Reg(11);
pub const a2: Reg = Reg(12);
pub const a3: Reg = Reg(13);
pub const a4: Reg = Reg(14);
pub const a5: Reg = Reg(15);
pub const a6: Reg = Reg(16);
pub const a7: Reg = Reg(17);
pub const s2: Reg = Reg(18);
pub const s3: Reg = Reg(19);
pub const s4: Reg = Reg(20);
pub const s5: Reg = Reg(21);
pub const s6: Reg = Reg(22);
pub const s7: Reg = Reg(23);
pub const s8: Reg = Reg(24);
pub const s9: Reg = Reg(25);
pub const s10: Reg = Reg(26);
pub const s11: Reg = Reg(27);
pub const t3: Reg = Reg(28);
pub const t4: Reg = Reg(29);
pub const t5: Reg = Reg(30);
pub const t6: Reg = Reg(31);
pub const ft0: Reg = Reg(0);
pub const ft1: Reg = Reg(1);
pub const ft2: Reg = Reg(2);
pub const ft3: Reg = Reg(3);
pub const ft4: Reg = Reg(4);
pub const ft5: Reg = Reg(5);
pub const ft6: Reg = Reg(6);
pub const ft7: Reg = Reg(7);
pub const fs0: Reg = Reg(8);
pub const fs1: Reg = Reg(9);
pub const fa0: Reg = Reg(10);
pub const fa1: Reg = Reg(11);
pub const fa2: Reg = Reg(12);
pub const fa3: Reg = Reg(13);
pub const fa4: Reg = Reg(14);
pub const fa5: Reg = Reg(15);
pub const fa6: Reg = Reg(16);
pub const fa7: Reg = Reg(17);
pub const fs2: Reg = Reg(18);
pub const fs3: Reg = Reg(19);
pub const fs4: Reg = Reg(20);
pub const fs5: Reg = Reg(21);
pub const fs6: Reg = Reg(22);
pub const fs7: Reg = Reg(23);
pub const fs8: Reg = Reg(24);
pub const fs9: Reg = Reg(25);
pub const fs10: Reg = Reg(26);
pub const fs11: Reg = Reg(27);
pub const ft8: Reg = Reg(28);
pub const ft9: Reg = Reg(29);
pub const ft10: Reg = Reg(30);
pub const ft11: Reg = Reg(31);
impl Reg {
#[inline]
pub const fn val(&self) -> u32 {
self.0 as u32
}
}