slices (offsets now real in backend)

src/ir/upper/func.rs

@@ -1,8 +1,8 @@
-use crate::compiler::arch::riscv64::Reg;
+use std::fmt::Write;
 
-use super::{arch::riscv64::RV64Instruction, DataID, FnID, VarID};
+use super::{arch::riscv64::RV64Instruction, DataID, FnID, Len, VarID};
+use crate::{compiler::arch::riscv64::Reg, util::Padder};
 
-#[derive(Debug)]
 pub struct IRUFunction {
     pub name: String,
     pub args: Vec<VarID>,
@@ -22,6 +22,11 @@ pub enum IRUInstruction {
         dest: VarID,
         src: DataID,
     },
+    LoadSlice {
+        dest: VarID,
+        src: DataID,
+        len: Len,
+    },
     LoadFn {
         dest: VarID,
         src: FnID,
@@ -70,6 +75,7 @@ impl std::fmt::Debug for IRUInstruction {
             Self::Ref { dest, src } => write!(f, "{dest:?} <- &{src:?}"),
             Self::LoadData { dest, src } => write!(f, "{dest:?} <- {src:?}"),
             Self::LoadFn { dest, src } => write!(f, "{dest:?} <- {src:?}"),
+            Self::LoadSlice { dest, src, len } => write!(f, "{dest:?} <- &[{src:?}; {len}]"),
             Self::Call {
                 dest,
                 f: func,
@@ -80,3 +86,21 @@ impl std::fmt::Debug for IRUInstruction {
         }
     }
 }
+
+impl std::fmt::Debug for IRUFunction {
+    fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result {
+        write!(f, "{}{:?}", &self.name, self.args)?;
+        if !self.instructions.is_empty() {
+            f.write_str("{\n    ")?;
+            let mut padder = Padder::new(f);
+            for i in &self.instructions {
+                // they don't expose wrap_buf :grief:
+                padder.write_str(&format!("{i:?};\n"))?;
+            }
+            f.write_char('}')?;
+        } else {
+            f.write_str("{}")?;
+        }
+        Ok(())
+    }
+}