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edit rex fn

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iris
2026-06-12 22:39:58 -04:00
parent 571ff70fa1
commit fa2a6db2e2
2 changed files with 44 additions and 22 deletions
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src/arch/x86_64/encode.rs
+5 -5
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@@ -40,14 +40,14 @@ impl Code {
if dst.width() == Width::B64 && src_width <= Width::B32 && src.0 < 0 {
// use different op that sign extends for less bytes
self.bytes
.extend([rex(dst.width(), 0, 0, dst), 0xc7, 0xc0 | dst.base()]);
.extend([rex(dst, 0, 0, dst), 0xc7, 0xc0 | dst.base()]);
self.imm(src, Width::B32);
} else {
if src_width <= Width::B32 {
dst = dst.lower64();
}
if dst.requires_rex() {
self.bytes.push(rex(dst.width(), 0, 0, dst));
self.bytes.push(rex(dst, 0, 0, dst));
}
self.bytes.push(0xb0 | (dst.not8() << 3) | dst.base());
self.imm(src, dst.width());
@@ -63,7 +63,7 @@ impl Code {
self.prefix32(&src)?;
self.prefix16(dst);
if dst.requires_rex() | src.reg.gt8() {
self.bytes.push(rex(dst.width(), dst, 0, src.reg));
self.bytes.push(rex(dst, dst, 0, src));
}
self.bytes.push(0x8a | dst.not8());
self.modrm_regdisp(dst, src);
@@ -80,7 +80,7 @@ impl Code {
self.prefix32(&dst)?;
self.prefix16(src);
if src.requires_rex() | dst.reg.gt8() {
self.bytes.push(rex(src.width(), src, 0, dst.reg));
self.bytes.push(rex(src, src, 0, dst));
}
self.bytes.push(0x88 | src.not8());
self.modrm_regdisp(src, dst);
@@ -101,7 +101,7 @@ impl Code {
self.prefix32(&dst)?;
self.prefix16(encode_width);
if dst.reg.requires_mem_rex() || dst.width == Width::B64 {
self.bytes.push(rex(dst.width, 0, 0, dst.reg));
self.bytes.push(rex(dst, 0, 0, dst));
}
self.bytes.push(0xc6 | encode_width.not8());
self.modrm_regdisp(None, dst);