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iris
2026-07-19 21:07:21 -04:00
parent 759af9a3d7
commit e4d2dcfe15
4 changed files with 64 additions and 101 deletions
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src/arch/x86_64/encode.rs
+11 -9
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@@ -11,10 +11,11 @@ pub struct Code {
}
impl Code {
pub fn mov(&mut self, dst: impl RegMem, src: impl Into<RegMemImm>) -> ERes {
pub fn mov(&mut self, dst: impl Into<RegMem>, src: impl Into<RegMemImm>) -> ERes {
let dst = dst.into();
let src = src.into();
match dst.kind() {
RegMemKind::Reg(mut dst) => match src {
match dst {
RegMem::Reg(mut dst) => match src {
RegMemImm::Reg(src) => {
if dst.width() != src.width() {
return Err("src and dst are not same width".into());
@@ -55,7 +56,7 @@ impl Code {
self.modrm(dst, src);
}
},
RegMemKind::Mem(dst) => match src {
RegMem::Mem(dst) => match src {
RegMemImm::Reg(src) => {
if src.width() != dst.width {
return Err("register & memory sizes don't match".into());
@@ -162,7 +163,8 @@ impl Code {
self.bytes.push(0xc3);
}
fn add_sub(&mut self, dst: impl RegMem, src: impl Into<RegMemImm>, ext: u8) -> ERes {
fn add_sub(&mut self, dst: impl Into<RegMem>, src: impl Into<RegMemImm>, ext: u8) -> ERes {
let dst = dst.into();
match src.into() {
RegMemImm::Reg(src) => {
if src.width() != dst.width() {
@@ -203,10 +205,10 @@ impl Code {
self.imm(src, imm_width);
}
RegMemImm::Mem(src) => {
let RegMemKind::Reg(dst) = dst.kind() else {
let RegMem::Reg(dst) = dst else {
return Err("cannot add memory to memory".into());
};
if src.width() != dst.width() {
if src.width != dst.width() {
return Err("incompatible widths".into());
}
self.prefix32(src)?;
@@ -219,11 +221,11 @@ impl Code {
Ok(())
}
pub fn add(&mut self, dst: impl RegMem, src: impl Into<RegMemImm>) -> ERes {
pub fn add(&mut self, dst: impl Into<RegMem>, src: impl Into<RegMemImm>) -> ERes {
self.add_sub(dst, src, 0)
}
pub fn sub(&mut self, dst: impl RegMem, src: impl Into<RegMemImm>) -> ERes {
pub fn sub(&mut self, dst: impl Into<RegMem>, src: impl Into<RegMemImm>) -> ERes {
self.add_sub(dst, src, 5)
}