work

src/arch/x86_64/encode.rs

@@ -1,7 +1,7 @@
 use super::*;
 use crate::backend::Symbol;
 
-type ERes = Result<(), CompilerMsg>;
+pub type EncodeRes = Result<(), CompilerMsg>;
 
 /// machine code
 #[derive(Default)]
@@ -11,7 +11,7 @@ pub struct Code {
 }
 
 impl Code {
-    pub fn mov(&mut self, dst: impl RegMem, src: impl Into<RegMemImm>) -> ERes {
+    pub fn mov(&mut self, dst: impl RegMem, src: impl Into<RegMemImm>) -> EncodeRes {
         let src = src.into();
         match dst.kind() {
             RegMemKind::Reg(mut dst) => match src {
@@ -92,7 +92,7 @@ impl Code {
         Ok(())
     }
 
-    pub fn push(&mut self, reg: impl Into<RegMemImm>) -> ERes {
+    pub fn push(&mut self, reg: impl Into<RegMemImm>) -> EncodeRes {
         match reg.into() {
             RegMemImm::Reg(reg) => match reg.width() {
                 Width::B64 => {
@@ -120,7 +120,7 @@ impl Code {
         Ok(())
     }
 
-    pub fn pop(&mut self, reg: Reg) -> ERes {
+    pub fn pop(&mut self, reg: RegW) -> EncodeRes {
         match reg.width() {
             Width::B64 | Width::B16 => (),
             _ => return Err("register must be 64 or 16 bit".into()),
@@ -133,7 +133,7 @@ impl Code {
         Ok(())
     }
 
-    pub fn lea(&mut self, dst: Reg, sym: Symbol) -> ERes {
+    pub fn lea(&mut self, dst: RegW, sym: Symbol) -> EncodeRes {
         self.rex(1, dst, 0, 0)?;
         self.bytes.push(0x8d);
         self.modrm(dst, sym);
@@ -162,7 +162,7 @@ impl Code {
         self.bytes.push(0xc3);
     }
 
-    fn add_sub(&mut self, dst: impl RegMem, src: impl Into<RegMemImm>, ext: u8) -> ERes {
+    fn add_sub(&mut self, dst: impl RegMem, src: impl Into<RegMemImm>, ext: u8) -> EncodeRes {
         match src.into() {
             RegMemImm::Reg(src) => {
                 if src.width() != dst.width() {
@@ -219,11 +219,11 @@ impl Code {
         Ok(())
     }
 
-    pub fn add(&mut self, dst: impl RegMem, src: impl Into<RegMemImm>) -> ERes {
+    pub fn add(&mut self, dst: impl RegMem, src: impl Into<RegMemImm>) -> EncodeRes {
         self.add_sub(dst, src, 0)
     }
 
-    pub fn sub(&mut self, dst: impl RegMem, src: impl Into<RegMemImm>) -> ERes {
+    pub fn sub(&mut self, dst: impl RegMem, src: impl Into<RegMemImm>) -> EncodeRes {
         self.add_sub(dst, src, 5)
     }
 
@@ -245,7 +245,7 @@ impl Code {
         Ok(())
     }
 
-    fn rex(&mut self, w: impl RexW, r: impl RexBit, x: u8, b: impl RexBit) -> ERes {
+    fn rex(&mut self, w: impl RexW, r: impl RexBit, x: u8, b: impl RexBit) -> EncodeRes {
         if r.req() && b.req_no() || r.req_no() && b.req() {
             return Err("registers incompatible (REX)".into());
         }