push and pop

src/arch/x86_64/reg.rs

@@ -16,16 +16,29 @@ pub enum BitWidth {
     B8,
 }
 
-impl RegMode {
+impl Reg {
     pub fn base(&self) -> u8 {
-        self.reg.0 & 0b111
+        self.0 & 0b111
     }
     /// checks if register is not one of the first 8 (0-7)
     pub fn gt8(&self) -> bool {
-        self.reg.0 >= 0b1000
+        self.0 >= 0b1000
     }
     pub fn gt4(&self) -> bool {
-        self.reg.0 >= 0b0100
+        self.0 >= 0b0100
+    }
+}
+
+impl RegMode {
+    pub fn base(&self) -> u8 {
+        self.reg.base()
+    }
+    /// checks if register is not one of the first 8 (0-7)
+    pub fn gt8(&self) -> bool {
+        self.reg.gt8()
+    }
+    pub fn gt4(&self) -> bool {
+        self.reg.gt4()
     }
 }