oop

src/arch/x86_64/compile.rs

@@ -72,7 +72,7 @@ pub struct RegUse {
 
 type BInstr = crate::backend::Instr<X86_64>;
 impl<'a> Encoder<'a> {
-    fn func(&mut self, f: &Func<X86_64>) -> EncodeRes {
+    fn func(&mut self, f: &Func<X86_64>) -> ERes {
         let addr = self.code.bytes.len();
         self.sym_tab.insert(f.sym, addr as u64);
         self.segs.clear();
@@ -207,7 +207,7 @@ impl<'a> Encoder<'a> {
         }
     }
 
-    pub fn asm(&mut self, asm: &Asm) -> EncodeRes {
+    pub fn asm(&mut self, asm: &Asm) -> ERes {
         let mut used = HashSet::default();
         let mut vars = HashSet::default();
         for &instr in &asm.instrs {

src/arch/x86_64/encode.rs

@@ -1,7 +1,7 @@
 use super::*;
 use crate::backend::Symbol;
 
-pub type EncodeRes = Result<(), CompilerMsg>;
+pub type ERes = Result<(), CompilerMsg>;
 
 /// machine code
 #[derive(Default)]
@@ -11,10 +11,9 @@ pub struct Code {
 }
 
 impl Code {
-    pub fn mov(&mut self, dst: impl Into<RegMemKind>, src: impl Into<RegMemImm>) -> EncodeRes {
+    pub fn mov(&mut self, dst: impl RegMem, src: impl Into<RegMemImm>) -> ERes {
         let src = src.into();
-        let dst = dst.into();
+        match dst.kind() {
-        match dst {
             RegMemKind::Reg(mut dst) => match src {
                 RegMemImm::Reg(src) => {
                     if dst.width() != src.width() {
@@ -93,7 +92,7 @@ impl Code {
         Ok(())
     }
 
-    pub fn push(&mut self, reg: impl Into<RegMemImm>) -> EncodeRes {
+    pub fn push(&mut self, reg: impl Into<RegMemImm>) -> ERes {
         match reg.into() {
             RegMemImm::Reg(reg) => match reg.width() {
                 Width::B64 => {
@@ -121,7 +120,7 @@ impl Code {
         Ok(())
     }
 
-    pub fn pop(&mut self, reg: RegW) -> EncodeRes {
+    pub fn pop(&mut self, reg: RegW) -> ERes {
         match reg.width() {
             Width::B64 | Width::B16 => (),
             _ => return Err("register must be 64 or 16 bit".into()),
@@ -134,7 +133,7 @@ impl Code {
         Ok(())
     }
 
-    pub fn lea(&mut self, dst: RegW, sym: Symbol) -> EncodeRes {
+    pub fn lea(&mut self, dst: RegW, sym: Symbol) -> ERes {
         self.rex(1, dst, 0, 0)?;
         self.bytes.push(0x8d);
         self.modrm(dst, sym);
@@ -163,13 +162,7 @@ impl Code {
         self.bytes.push(0xc3);
     }
 
-    fn add_sub(
+    fn add_sub(&mut self, dst: impl RegMem, src: impl Into<RegMemImm>, ext: u8) -> ERes {
-        &mut self,
-        dst: impl Into<RegMemKind>,
-        src: impl Into<RegMemImm>,
-        ext: u8,
-    ) -> EncodeRes {
-        let dst = dst.into();
         match src.into() {
             RegMemImm::Reg(src) => {
                 if src.width() != dst.width() {
@@ -226,11 +219,11 @@ impl Code {
         Ok(())
     }
 
-    pub fn add(&mut self, dst: impl Into<RegMemKind>, src: impl Into<RegMemImm>) -> EncodeRes {
+    pub fn add(&mut self, dst: impl RegMem, src: impl Into<RegMemImm>) -> ERes {
         self.add_sub(dst, src, 0)
     }
 
-    pub fn sub(&mut self, dst: impl Into<RegMemKind>, src: impl Into<RegMemImm>) -> EncodeRes {
+    pub fn sub(&mut self, dst: impl RegMem, src: impl Into<RegMemImm>) -> ERes {
         self.add_sub(dst, src, 5)
     }
 
@@ -252,7 +245,7 @@ impl Code {
         Ok(())
     }
 
-    fn rex(&mut self, w: impl RexW, r: impl RexBit, x: u8, b: impl RexBit) -> EncodeRes {
+    fn rex(&mut self, w: impl RexW, r: impl RexBit, x: u8, b: impl RexBit) -> ERes {
         if r.req() && b.req_no() || r.req_no() && b.req() {
             return Err("registers incompatible (REX)".into());
         }

src/arch/x86_64/types/arg.rs

@@ -1,6 +1,11 @@
 use super::*;
 use crate::backend::Symbol;
 
+pub trait RegMem: RexBit + RexW + ModRMRM + Copy + MaybeMem {
+    fn width(&self) -> Width;
+    fn kind(self) -> RegMemKind;
+}
+
 #[derive(Clone, Copy)]
 pub enum RegMemKind {
     Reg(RegW),
@@ -18,12 +23,12 @@ pub trait MaybeMem {
     fn mem(&self) -> Option<Mem>;
 }
 
-impl RegMemKind {
+impl RegMem for RegW {
-    pub fn width(&self) -> Width {
+    fn width(&self) -> Width {
-        match self {
+        self.width()
-            RegMemKind::Reg(reg) => reg.width(),
-            RegMemKind::Mem(mem) => todo!(),
     }
+    fn kind(self) -> RegMemKind {
+        RegMemKind::Reg(self)
     }
 }