diff --git a/src/arch/x86_64/encode.rs b/src/arch/x86_64/encode.rs
index 29a64b1..684a298 100644
--- a/src/arch/x86_64/encode.rs
+++ b/src/arch/x86_64/encode.rs
@@ -190,7 +190,7 @@ impl Code {
             _ => 0b10,
         };
         self.bytes.push(modrm(mod_, 0, reg.base()));
-        if reg.val() == rsp.val() {
+        if reg.base() == rsp.base() {
             // SIB
             self.bytes.push(0x24);
         }
diff --git a/src/arch/x86_64/reg.rs b/src/arch/x86_64/reg.rs
index 8906300..5ae18a8 100644
--- a/src/arch/x86_64/reg.rs
+++ b/src/arch/x86_64/reg.rs
@@ -29,10 +29,10 @@ def_regs! {
     0b1001 : r9  r9d  r9w  r9b !_,
     0b1010 : r10 r10d r10w r10b,
     0b1011 : r11 r11d r11w r11b,
-    0b1100 : r12 r12d r12w r12b,
+    0b1100 : r12 r12d r12w r12b !_,
     0b1101 : r13 r13d r13w r13b,
     0b1110 : r14 r14d r14w r14b,
-    0b1111 : r15 r15d r15w r15b !_,
+    0b1111 : r15 r15d r15w r15b,
 }
 
 impl Reg {
@@ -46,13 +46,6 @@ impl Reg {
     pub fn gt4(&self) -> bool {
         self.val >= 0b0100
     }
-    pub fn high(&self) -> bool {
-        self.high
-    }
-
-    pub fn val(&self) -> u8 {
-        self.val
-    }
 
     pub fn width(&self) -> Width {
         self.width
@@ -165,10 +158,10 @@ macro_rules! def_regs {
         )*
 
         impl Reg {
-            #[cfg(test)]
-            pub const ALL: &[Reg] = &[
-                $( $B64, $B32, $B16, $B8, $($B8H,)? )*
-            ];
+            // #[cfg(test)]
+            // pub const ALL: &[Reg] = &[
+            //     $( $B64, $B32, $B16, $B8, $($B8H,)? )*
+            // ];
 
             #[cfg(test)]
             pub const IMPORTANT: &[Reg] = &