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iris
2025-05-04 04:12:56 -04:00
parent 5f36be9de9
commit 6583d47ef8
23 changed files with 1261 additions and 740 deletions
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src/parser/v3/lower/asm.rs
+4 -3
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@@ -1,14 +1,15 @@
use crate::{
compiler::arch::riscv::Reg,
ir::{
arch::riscv64::RV64Instruction, AsmBlockArg, AsmBlockArgType, Type, UInstruction, VarInst
arch::riscv64::RV64Instruction, AsmBlockArg, AsmBlockArgType, Type, UInstruction, VarInst,
VarInstID,
},
parser::PAsmBlockArg,
};
use super::{FnLowerCtx, FnLowerable, PAsmBlock, PInstruction, PUAsmBlockArg};
type PLAsmBlockArg = PAsmBlockArg<Reg, VarInst>;
type PLAsmBlockArg = PAsmBlockArg<Reg, VarInstID>;
impl FnLowerable for PInstruction {
type Output = RV64Instruction;
@@ -19,7 +20,7 @@ impl FnLowerable for PInstruction {
}
impl FnLowerable for PAsmBlock {
type Output = VarInst;
type Output = VarInstID;
fn lower(&self, ctx: &mut FnLowerCtx) -> Option<Self::Output> {
let mut args = Vec::new();