diff --git a/src/arch/x86_64/encode.rs b/src/arch/x86_64/encode.rs
index 482cedc..6612100 100644
--- a/src/arch/x86_64/encode.rs
+++ b/src/arch/x86_64/encode.rs
@@ -11,11 +11,11 @@ pub struct Code {
 }
 
 impl Code {
-    pub fn mov(&mut self, dst: impl RegMem, src: impl Into<RegImmMem>) -> ERes {
+    pub fn mov(&mut self, dst: impl RegMem, src: impl Into<RegMemImm>) -> ERes {
         let src = src.into();
         match dst.kind() {
             RegMemKind::Reg(mut dst) => match src {
-                RegImmMem::Reg(src) => {
+                RegMemImm::Reg(src) => {
                     if dst.width() != src.width() {
                         return Err("src and dst are not same width".into());
                     }
@@ -27,7 +27,7 @@ impl Code {
                     self.bytes.push(0x88 | dst.not8());
                     self.modrm(src, dst);
                 }
-                RegImmMem::Imm(src) => {
+                RegMemImm::Imm(src) => {
                     let src_width = src.width_unsigned()?;
                     if src_width > dst.width() {
                         return Err("immediate cannot fit in register".into());
@@ -47,7 +47,7 @@ impl Code {
                         self.imm(src, dst.width());
                     }
                 }
-                RegImmMem::Mem(src) => {
+                RegMemImm::Mem(src) => {
                     if src.width != dst.width() {
                         return Err("register & memory sizes don't match".into());
                     }
@@ -62,7 +62,7 @@ impl Code {
                 }
             },
             RegMemKind::Mem(dst) => match src {
-                RegImmMem::Reg(src) => {
+                RegMemImm::Reg(src) => {
                     if src.width() != dst.width {
                         return Err("register & memory sizes don't match".into());
                     }
@@ -75,7 +75,7 @@ impl Code {
                     self.bytes.push(0x88 | src.not8());
                     self.modrm(src, dst);
                 }
-                RegImmMem::Imm(src) => {
+                RegMemImm::Imm(src) => {
                     let encode_width = dst.width.min(Width::B32);
                     let src_width = if dst.width == Width::B64 {
                         src.width_signed()
@@ -95,15 +95,15 @@ impl Code {
                     self.modrm(0, dst);
                     self.imm(src, encode_width);
                 }
-                RegImmMem::Mem(_) => return Err("cannot move memory to memory".into()),
+                RegMemImm::Mem(_) => return Err("cannot move memory to memory".into()),
             },
         }
         Ok(())
     }
 
-    pub fn push(&mut self, reg: impl Into<RegImmMem>) -> ERes {
+    pub fn push(&mut self, reg: impl Into<RegMemImm>) -> ERes {
         match reg.into() {
-            RegImmMem::Reg(reg) => match reg.width() {
+            RegMemImm::Reg(reg) => match reg.width() {
                 Width::B64 => {
                     if reg.gt8() {
                         self.bytes.push(0x41);
@@ -113,7 +113,7 @@ impl Code {
                 Width::B16 => todo!(),
                 _ => return Err("register must be 64 or 16 bit".into()),
             },
-            RegImmMem::Imm(imm) => match imm.width_unsigned()? {
+            RegMemImm::Imm(imm) => match imm.width_unsigned()? {
                 Width::B8 => {
                     self.bytes.push(0x6a);
                     self.bytes.push(imm.0 as u8);
@@ -124,7 +124,7 @@ impl Code {
                 }
                 Width::B64 => return Err("immediate must be 32 bit or less".into()),
             },
-            RegImmMem::Mem(mem) => todo!(),
+            RegMemImm::Mem(mem) => todo!(),
         }
         Ok(())
     }
diff --git a/src/arch/x86_64/types/arg.rs b/src/arch/x86_64/types/arg.rs
index a81eb42..2c466b9 100644
--- a/src/arch/x86_64/types/arg.rs
+++ b/src/arch/x86_64/types/arg.rs
@@ -1,11 +1,9 @@
 use super::*;
 use crate::backend::Symbol;
 
-#[derive(Clone, Copy)]
-pub enum RegImmMem {
-    Reg(Reg),
-    Imm(Imm),
-    Mem(Mem),
+pub trait RegMem: RexBit + RexW + ModRMRM + Copy + MaybeMem {
+    fn width(&self) -> Width;
+    fn kind(self) -> RegMemKind;
 }
 
 #[derive(Clone, Copy)]
@@ -14,9 +12,11 @@ pub enum RegMemKind {
     Mem(Mem),
 }
 
-pub trait RegMem: RexBit + RexW + ModRMRM + Copy + MaybeMem {
-    fn width(&self) -> Width;
-    fn kind(self) -> RegMemKind;
+#[derive(Clone, Copy)]
+pub enum RegMemImm {
+    Reg(Reg),
+    Imm(Imm),
+    Mem(Mem),
 }
 
 pub trait MaybeMem {
@@ -54,7 +54,7 @@ impl MaybeMem for Mem {
 }
 
 // fromrot
-impl From<Reg> for RegImmMem {
+impl From<Reg> for RegMemImm {
     fn from(value: Reg) -> Self {
         Self::Reg(value)
     }
@@ -66,7 +66,7 @@ impl From<Reg> for RegMemKind {
     }
 }
 
-impl From<Mem> for RegImmMem {
+impl From<Mem> for RegMemImm {
     fn from(value: Mem) -> Self {
         Self::Mem(value)
     }
@@ -78,25 +78,25 @@ impl From<Mem> for RegMemKind {
     }
 }
 
-impl From<u64> for RegImmMem {
+impl From<u64> for RegMemImm {
     fn from(value: u64) -> Self {
         Self::Imm(value.into())
     }
 }
 
-impl From<i64> for RegImmMem {
+impl From<i64> for RegMemImm {
     fn from(value: i64) -> Self {
         Self::Imm(value.into())
     }
 }
 
-impl From<i32> for RegImmMem {
+impl From<i32> for RegMemImm {
     fn from(value: i32) -> Self {
         Self::Imm(value.into())
     }
 }
 
-impl From<i128> for RegImmMem {
+impl From<i128> for RegMemImm {
     fn from(value: i128) -> Self {
         Self::Imm(value.into())
     }
diff --git a/src/parser/nodes/asm/x86_64.rs b/src/parser/nodes/asm/x86_64.rs
index 6bef902..65716c0 100644
--- a/src/parser/nodes/asm/x86_64.rs
+++ b/src/parser/nodes/asm/x86_64.rs
@@ -64,12 +64,12 @@ pub fn parse_imm(mut s: &str, span: Span) -> Result<Imm, CompilerMsg> {
     Ok(Imm(val))
 }
 
-pub fn parse_rmi(ctx: &mut crate::parser::ParseCtx) -> Result<RegImmMem, CompilerMsg> {
+pub fn parse_rmi(ctx: &mut crate::parser::ParseCtx) -> Result<RegMemImm, CompilerMsg> {
     let next = ctx.expect_next()?;
     let err = || CompilerMsg::unexpected_token(&next, ctx.span, "a register or immediate");
     Ok(match &next {
-        Token::Ident(ident) => RegImmMem::Reg(Reg::parse(ident).ok_or_else(err)?),
-        Token::Lit(LitTy::Number(num)) => RegImmMem::Imm(parse_imm(num, ctx.span)?),
+        Token::Ident(ident) => RegMemImm::Reg(Reg::parse(ident).ok_or_else(err)?),
+        Token::Lit(LitTy::Number(num)) => RegMemImm::Imm(parse_imm(num, ctx.span)?),
         _ => return Err(err()),
     })
 }